1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s 2 3 ; PR11102 4 define <4 x float> @test1(<4 x float> %a) nounwind { 5 %b = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 2, i32 5, i32 undef, i32 undef> 6 ret <4 x float> %b 7 ; CHECK: test1: 8 ; CHECK: vshufps 9 ; CHECK: vpermilps 10 } 11 12 ; rdar://10538417 13 define <3 x i64> @test2(<2 x i64> %v) nounwind readnone { 14 ; CHECK: test2: 15 ; CHECK: vinsertf128 16 %1 = shufflevector <2 x i64> %v, <2 x i64> %v, <3 x i32> <i32 0, i32 1, i32 undef> 17 %2 = shufflevector <3 x i64> zeroinitializer, <3 x i64> %1, <3 x i32> <i32 3, i32 4, i32 2> 18 ret <3 x i64> %2 19 ; CHECK: ret 20 } 21 22 define <4 x i64> @test3(<4 x i64> %a, <4 x i64> %b) nounwind { 23 %c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 4, i32 5, i32 2, i32 undef> 24 ret <4 x i64> %c 25 ; CHECK: test3: 26 ; CHECK: vperm2f128 27 ; CHECK: ret 28 } 29 30 define <8 x float> @test4(float %a) nounwind { 31 %b = insertelement <8 x float> zeroinitializer, float %a, i32 0 32 ret <8 x float> %b 33 ; CHECK: test4: 34 ; CHECK: vinsertf128 35 } 36 37 ; rdar://10594409 38 define <8 x float> @test5(float* nocapture %f) nounwind uwtable readonly ssp { 39 entry: 40 %0 = bitcast float* %f to <4 x float>* 41 %1 = load <4 x float>* %0, align 16 42 ; CHECK: test5 43 ; CHECK: vmovaps 44 ; CHECK-NOT: vxorps 45 ; CHECK-NOT: vinsertf128 46 %shuffle.i = shufflevector <4 x float> %1, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 4, i32 4> 47 ret <8 x float> %shuffle.i 48 } 49 50 define <4 x double> @test6(double* nocapture %d) nounwind uwtable readonly ssp { 51 entry: 52 %0 = bitcast double* %d to <2 x double>* 53 %1 = load <2 x double>* %0, align 16 54 ; CHECK: test6 55 ; CHECK: vmovaps 56 ; CHECK-NOT: vxorps 57 ; CHECK-NOT: vinsertf128 58 %shuffle.i = shufflevector <2 x double> %1, <2 x double> <double 0.000000e+00, double undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 2> 59 ret <4 x double> %shuffle.i 60 } 61 62 define <16 x i16> @test7(<4 x i16> %a) nounwind { 63 ; CHECK: test7 64 %b = shufflevector <4 x i16> %a, <4 x i16> undef, <16 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> 65 ; CHECK: ret 66 ret <16 x i16> %b 67 } 68 69 ; CHECK: test8 70 define void @test8() { 71 entry: 72 %0 = load <16 x i64> addrspace(1)* null, align 128 73 %1 = shufflevector <16 x i64> <i64 undef, i64 undef, i64 0, i64 undef, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 undef, i64 0, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i64> %0, <16 x i32> <i32 17, i32 18, i32 2, i32 undef, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 undef, i32 11, i32 undef, i32 undef, i32 undef, i32 26> 74 %2 = shufflevector <16 x i64> %1, <16 x i64> %0, <16 x i32> <i32 0, i32 1, i32 2, i32 30, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 undef, i32 11, i32 undef, i32 22, i32 20, i32 15> 75 store <16 x i64> %2, <16 x i64> addrspace(1)* undef, align 128 76 ; CHECK: ret 77 ret void 78 } 79 80 ; Extract a value from a shufflevector.. 81 define i32 @test9(<4 x i32> %a) nounwind { 82 ; CHECK: test9 83 ; CHECK: vpextrd 84 %b = shufflevector <4 x i32> %a, <4 x i32> undef, <8 x i32> <i32 1, i32 1, i32 2, i32 2, i32 3, i32 3, i32 undef, i32 4> 85 %r = extractelement <8 x i32> %b, i32 2 86 ; CHECK: ret 87 ret i32 %r 88 } 89 90 ; Extract a value which is the result of an undef mask. 91 define i32 @test10(<4 x i32> %a) nounwind { 92 ; CHECK: @test10 93 ; CHECK-NEXT: # 94 ; CHECK-NEXT: ret 95 %b = shufflevector <4 x i32> %a, <4 x i32> undef, <8 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> 96 %r = extractelement <8 x i32> %b, i32 2 97 ret i32 %r 98 } 99 100 define <4 x float> @test11(<4 x float> %a) nounwind { 101 ; check: test11 102 ; check: vpermilps $27 103 %tmp1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> 104 ret <4 x float> %tmp1 105 } 106 107 define <4 x float> @test12(<4 x float>* %a) nounwind { 108 ; CHECK: test12 109 ; CHECK: vpermilps $27, ( 110 %tmp0 = load <4 x float>* %a 111 %tmp1 = shufflevector <4 x float> %tmp0, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> 112 ret <4 x float> %tmp1 113 } 114 115 define <4 x i32> @test13(<4 x i32> %a) nounwind { 116 ; check: test13 117 ; check: vpshufd $27 118 %tmp1 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> 119 ret <4 x i32> %tmp1 120 } 121 122 define <4 x i32> @test14(<4 x i32>* %a) nounwind { 123 ; CHECK: test14 124 ; CHECK: vpshufd $27, ( 125 %tmp0 = load <4 x i32>* %a 126 %tmp1 = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> 127 ret <4 x i32> %tmp1 128 } 129 130 ; CHECK: test15 131 ; CHECK: vpshufd $8 132 ; CHECK: ret 133 define <4 x i32> @test15(<2 x i32>%x) nounwind readnone { 134 %x1 = shufflevector <2 x i32> %x, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> 135 ret <4 x i32>%x1 136 } 137 138 ; rdar://10974078 139 define <8 x float> @test16(float* nocapture %f) nounwind uwtable readonly ssp { 140 entry: 141 %0 = bitcast float* %f to <4 x float>* 142 %1 = load <4 x float>* %0, align 8 143 ; CHECK: test16 144 ; CHECK: vmovups 145 ; CHECK-NOT: vxorps 146 ; CHECK-NOT: vinsertf128 147 %shuffle.i = shufflevector <4 x float> %1, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 4, i32 4> 148 ret <8 x float> %shuffle.i 149 } 150 151 ; PR12413 152 ; CHECK: vpshufb 153 ; CHECK: vpshufb 154 ; CHECK: vpshufb 155 ; CHECK: vpshufb 156 define <32 x i8> @shuf(<32 x i8> %inval1, <32 x i8> %inval2) { 157 entry: 158 %0 = shufflevector <32 x i8> %inval1, <32 x i8> %inval2, <32 x i32> <i32 0, 159 i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 160 22, i32 24, i32 26, i32 28, i32 30, i32 32, i32 34, i32 36, i32 38, i32 40, i32 161 42, i32 44, i32 46, i32 48, i32 50, i32 52, i32 54, i32 56, i32 58, i32 60, i32 162 62> 163 ret <32 x i8> %0 164 } 165 166 ; CHECK: blend1 167 ; CHECK: vblendps 168 ; CHECK: ret 169 define <4 x i32> @blend1(<4 x i32> %a, <4 x i32> %b) nounwind alwaysinline { 170 %t = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7> 171 ret <4 x i32> %t 172 } 173 174 ; CHECK: blend2 175 ; CHECK: vblendps 176 ; CHECK: ret 177 define <4 x i32> @blend2(<4 x i32> %a, <4 x i32> %b) nounwind alwaysinline { 178 %t = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7> 179 ret <4 x i32> %t 180 } 181 182 ; CHECK: blend2a 183 ; CHECK: vblendps 184 ; CHECK: ret 185 define <4 x float> @blend2a(<4 x float> %a, <4 x float> %b) nounwind alwaysinline { 186 %t = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7> 187 ret <4 x float> %t 188 } 189 190 ; CHECK: blend3 191 ; CHECK-NOT: vblendps 192 ; CHECK: ret 193 define <4 x i32> @blend3(<4 x i32> %a, <4 x i32> %b) nounwind alwaysinline { 194 %t = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 5, i32 2, i32 7> 195 ret <4 x i32> %t 196 } 197 198 ; CHECK: blend4 199 ; CHECK: vblendpd 200 ; CHECK: ret 201 define <4 x i64> @blend4(<4 x i64> %a, <4 x i64> %b) nounwind alwaysinline { 202 %t = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7> 203 ret <4 x i64> %t 204 } 205
