1 //===- EDEmitter.cpp - Generate instruction descriptions for ED -*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This tablegen backend is responsible for emitting a description of each 11 // instruction in a format that the enhanced disassembler can use to tokenize 12 // and parse instructions. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "EDEmitter.h" 17 18 #include "AsmWriterInst.h" 19 #include "CodeGenTarget.h" 20 21 #include "llvm/TableGen/Record.h" 22 #include "llvm/MC/EDInstInfo.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/Format.h" 25 #include "llvm/Support/raw_ostream.h" 26 27 #include <string> 28 #include <vector> 29 30 using namespace llvm; 31 32 /////////////////////////////////////////////////////////// 33 // Support classes for emitting nested C data structures // 34 /////////////////////////////////////////////////////////// 35 36 namespace { 37 38 class EnumEmitter { 39 private: 40 std::string Name; 41 std::vector<std::string> Entries; 42 public: 43 EnumEmitter(const char *N) : Name(N) { 44 } 45 int addEntry(const char *e) { 46 Entries.push_back(std::string(e)); 47 return Entries.size() - 1; 48 } 49 void emit(raw_ostream &o, unsigned int &i) { 50 o.indent(i) << "enum " << Name.c_str() << " {" << "\n"; 51 i += 2; 52 53 unsigned int index = 0; 54 unsigned int numEntries = Entries.size(); 55 for (index = 0; index < numEntries; ++index) { 56 o.indent(i) << Entries[index]; 57 if (index < (numEntries - 1)) 58 o << ","; 59 o << "\n"; 60 } 61 62 i -= 2; 63 o.indent(i) << "};" << "\n"; 64 } 65 66 void emitAsFlags(raw_ostream &o, unsigned int &i) { 67 o.indent(i) << "enum " << Name.c_str() << " {" << "\n"; 68 i += 2; 69 70 unsigned int index = 0; 71 unsigned int numEntries = Entries.size(); 72 unsigned int flag = 1; 73 for (index = 0; index < numEntries; ++index) { 74 o.indent(i) << Entries[index] << " = " << format("0x%x", flag); 75 if (index < (numEntries - 1)) 76 o << ","; 77 o << "\n"; 78 flag <<= 1; 79 } 80 81 i -= 2; 82 o.indent(i) << "};" << "\n"; 83 } 84 }; 85 86 class ConstantEmitter { 87 public: 88 virtual ~ConstantEmitter() { } 89 virtual void emit(raw_ostream &o, unsigned int &i) = 0; 90 }; 91 92 class LiteralConstantEmitter : public ConstantEmitter { 93 private: 94 bool IsNumber; 95 union { 96 int Number; 97 const char* String; 98 }; 99 public: 100 LiteralConstantEmitter(int number = 0) : 101 IsNumber(true), 102 Number(number) { 103 } 104 void set(const char *string) { 105 IsNumber = false; 106 Number = 0; 107 String = string; 108 } 109 bool is(const char *string) { 110 return !strcmp(String, string); 111 } 112 void emit(raw_ostream &o, unsigned int &i) { 113 if (IsNumber) 114 o << Number; 115 else 116 o << String; 117 } 118 }; 119 120 class CompoundConstantEmitter : public ConstantEmitter { 121 private: 122 unsigned int Padding; 123 std::vector<ConstantEmitter *> Entries; 124 public: 125 CompoundConstantEmitter(unsigned int padding = 0) : Padding(padding) { 126 } 127 CompoundConstantEmitter &addEntry(ConstantEmitter *e) { 128 Entries.push_back(e); 129 130 return *this; 131 } 132 ~CompoundConstantEmitter() { 133 while (Entries.size()) { 134 ConstantEmitter *entry = Entries.back(); 135 Entries.pop_back(); 136 delete entry; 137 } 138 } 139 void emit(raw_ostream &o, unsigned int &i) { 140 o << "{" << "\n"; 141 i += 2; 142 143 unsigned int index; 144 unsigned int numEntries = Entries.size(); 145 146 unsigned int numToPrint; 147 148 if (Padding) { 149 if (numEntries > Padding) { 150 fprintf(stderr, "%u entries but %u padding\n", numEntries, Padding); 151 llvm_unreachable("More entries than padding"); 152 } 153 numToPrint = Padding; 154 } else { 155 numToPrint = numEntries; 156 } 157 158 for (index = 0; index < numToPrint; ++index) { 159 o.indent(i); 160 if (index < numEntries) 161 Entries[index]->emit(o, i); 162 else 163 o << "-1"; 164 165 if (index < (numToPrint - 1)) 166 o << ","; 167 o << "\n"; 168 } 169 170 i -= 2; 171 o.indent(i) << "}"; 172 } 173 }; 174 175 class FlagsConstantEmitter : public ConstantEmitter { 176 private: 177 std::vector<std::string> Flags; 178 public: 179 FlagsConstantEmitter() { 180 } 181 FlagsConstantEmitter &addEntry(const char *f) { 182 Flags.push_back(std::string(f)); 183 return *this; 184 } 185 void emit(raw_ostream &o, unsigned int &i) { 186 unsigned int index; 187 unsigned int numFlags = Flags.size(); 188 if (numFlags == 0) 189 o << "0"; 190 191 for (index = 0; index < numFlags; ++index) { 192 o << Flags[index].c_str(); 193 if (index < (numFlags - 1)) 194 o << " | "; 195 } 196 } 197 }; 198 } 199 200 EDEmitter::EDEmitter(RecordKeeper &R) : Records(R) { 201 } 202 203 /// populateOperandOrder - Accepts a CodeGenInstruction and generates its 204 /// AsmWriterInst for the desired assembly syntax, giving an ordered list of 205 /// operands in the order they appear in the printed instruction. Then, for 206 /// each entry in that list, determines the index of the same operand in the 207 /// CodeGenInstruction, and emits the resulting mapping into an array, filling 208 /// in unused slots with -1. 209 /// 210 /// @arg operandOrder - The array that will be populated with the operand 211 /// mapping. Each entry will contain -1 (invalid index 212 /// into the operands present in the AsmString) or a number 213 /// representing an index in the operand descriptor array. 214 /// @arg inst - The instruction to use when looking up the operands 215 /// @arg syntax - The syntax to use, according to LLVM's enumeration 216 void populateOperandOrder(CompoundConstantEmitter *operandOrder, 217 const CodeGenInstruction &inst, 218 unsigned syntax) { 219 unsigned int numArgs = 0; 220 221 AsmWriterInst awInst(inst, syntax, -1, -1); 222 223 std::vector<AsmWriterOperand>::iterator operandIterator; 224 225 for (operandIterator = awInst.Operands.begin(); 226 operandIterator != awInst.Operands.end(); 227 ++operandIterator) { 228 if (operandIterator->OperandType == 229 AsmWriterOperand::isMachineInstrOperand) { 230 operandOrder->addEntry( 231 new LiteralConstantEmitter(operandIterator->CGIOpNo)); 232 numArgs++; 233 } 234 } 235 } 236 237 ///////////////////////////////////////////////////// 238 // Support functions for handling X86 instructions // 239 ///////////////////////////////////////////////////// 240 241 #define SET(flag) { type->set(flag); return 0; } 242 243 #define REG(str) if (name == str) SET("kOperandTypeRegister"); 244 #define MEM(str) if (name == str) SET("kOperandTypeX86Memory"); 245 #define LEA(str) if (name == str) SET("kOperandTypeX86EffectiveAddress"); 246 #define IMM(str) if (name == str) SET("kOperandTypeImmediate"); 247 #define PCR(str) if (name == str) SET("kOperandTypeX86PCRelative"); 248 249 /// X86TypeFromOpName - Processes the name of a single X86 operand (which is 250 /// actually its type) and translates it into an operand type 251 /// 252 /// @arg flags - The type object to set 253 /// @arg name - The name of the operand 254 static int X86TypeFromOpName(LiteralConstantEmitter *type, 255 const std::string &name) { 256 REG("GR8"); 257 REG("GR8_NOREX"); 258 REG("GR16"); 259 REG("GR16_NOAX"); 260 REG("GR32"); 261 REG("GR32_NOAX"); 262 REG("GR32_NOREX"); 263 REG("GR32_TC"); 264 REG("FR32"); 265 REG("RFP32"); 266 REG("GR64"); 267 REG("GR64_NOAX"); 268 REG("GR64_TC"); 269 REG("FR64"); 270 REG("VR64"); 271 REG("RFP64"); 272 REG("RFP80"); 273 REG("VR128"); 274 REG("VR256"); 275 REG("RST"); 276 REG("SEGMENT_REG"); 277 REG("DEBUG_REG"); 278 REG("CONTROL_REG"); 279 280 IMM("i8imm"); 281 IMM("i16imm"); 282 IMM("i16i8imm"); 283 IMM("i32imm"); 284 IMM("i32i8imm"); 285 IMM("u32u8imm"); 286 IMM("i64imm"); 287 IMM("i64i8imm"); 288 IMM("i64i32imm"); 289 IMM("SSECC"); 290 IMM("AVXCC"); 291 292 // all R, I, R, I, R 293 MEM("i8mem"); 294 MEM("i8mem_NOREX"); 295 MEM("i16mem"); 296 MEM("i32mem"); 297 MEM("i32mem_TC"); 298 MEM("f32mem"); 299 MEM("ssmem"); 300 MEM("opaque32mem"); 301 MEM("opaque48mem"); 302 MEM("i64mem"); 303 MEM("i64mem_TC"); 304 MEM("f64mem"); 305 MEM("sdmem"); 306 MEM("f80mem"); 307 MEM("opaque80mem"); 308 MEM("i128mem"); 309 MEM("i256mem"); 310 MEM("f128mem"); 311 MEM("f256mem"); 312 MEM("opaque512mem"); 313 314 // all R, I, R, I 315 LEA("lea32mem"); 316 LEA("lea64_32mem"); 317 LEA("lea64mem"); 318 319 // all I 320 PCR("i16imm_pcrel"); 321 PCR("i32imm_pcrel"); 322 PCR("i64i32imm_pcrel"); 323 PCR("brtarget8"); 324 PCR("offset8"); 325 PCR("offset16"); 326 PCR("offset32"); 327 PCR("offset64"); 328 PCR("brtarget"); 329 PCR("uncondbrtarget"); 330 PCR("bltarget"); 331 332 // all I, ARM mode only, conditional/unconditional 333 PCR("br_target"); 334 PCR("bl_target"); 335 return 1; 336 } 337 338 #undef REG 339 #undef MEM 340 #undef LEA 341 #undef IMM 342 #undef PCR 343 344 #undef SET 345 346 /// X86PopulateOperands - Handles all the operands in an X86 instruction, adding 347 /// the appropriate flags to their descriptors 348 /// 349 /// @operandFlags - A reference the array of operand flag objects 350 /// @inst - The instruction to use as a source of information 351 static void X86PopulateOperands( 352 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS], 353 const CodeGenInstruction &inst) { 354 if (!inst.TheDef->isSubClassOf("X86Inst")) 355 return; 356 357 unsigned int index; 358 unsigned int numOperands = inst.Operands.size(); 359 360 for (index = 0; index < numOperands; ++index) { 361 const CGIOperandList::OperandInfo &operandInfo = inst.Operands[index]; 362 Record &rec = *operandInfo.Rec; 363 364 if (X86TypeFromOpName(operandTypes[index], rec.getName()) && 365 !rec.isSubClassOf("PointerLikeRegClass")) { 366 errs() << "Operand type: " << rec.getName().c_str() << "\n"; 367 errs() << "Operand name: " << operandInfo.Name.c_str() << "\n"; 368 errs() << "Instruction name: " << inst.TheDef->getName().c_str() << "\n"; 369 llvm_unreachable("Unhandled type"); 370 } 371 } 372 } 373 374 /// decorate1 - Decorates a named operand with a new flag 375 /// 376 /// @operandFlags - The array of operand flag objects, which don't have names 377 /// @inst - The CodeGenInstruction, which provides a way to translate 378 /// between names and operand indices 379 /// @opName - The name of the operand 380 /// @flag - The name of the flag to add 381 static inline void decorate1( 382 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS], 383 const CodeGenInstruction &inst, 384 const char *opName, 385 const char *opFlag) { 386 unsigned opIndex; 387 388 opIndex = inst.Operands.getOperandNamed(std::string(opName)); 389 390 operandFlags[opIndex]->addEntry(opFlag); 391 } 392 393 #define DECORATE1(opName, opFlag) decorate1(operandFlags, inst, opName, opFlag) 394 395 #define MOV(source, target) { \ 396 instType.set("kInstructionTypeMove"); \ 397 DECORATE1(source, "kOperandFlagSource"); \ 398 DECORATE1(target, "kOperandFlagTarget"); \ 399 } 400 401 #define BRANCH(target) { \ 402 instType.set("kInstructionTypeBranch"); \ 403 DECORATE1(target, "kOperandFlagTarget"); \ 404 } 405 406 #define PUSH(source) { \ 407 instType.set("kInstructionTypePush"); \ 408 DECORATE1(source, "kOperandFlagSource"); \ 409 } 410 411 #define POP(target) { \ 412 instType.set("kInstructionTypePop"); \ 413 DECORATE1(target, "kOperandFlagTarget"); \ 414 } 415 416 #define CALL(target) { \ 417 instType.set("kInstructionTypeCall"); \ 418 DECORATE1(target, "kOperandFlagTarget"); \ 419 } 420 421 #define RETURN() { \ 422 instType.set("kInstructionTypeReturn"); \ 423 } 424 425 /// X86ExtractSemantics - Performs various checks on the name of an X86 426 /// instruction to determine what sort of an instruction it is and then adds 427 /// the appropriate flags to the instruction and its operands 428 /// 429 /// @arg instType - A reference to the type for the instruction as a whole 430 /// @arg operandFlags - A reference to the array of operand flag object pointers 431 /// @arg inst - A reference to the original instruction 432 static void X86ExtractSemantics( 433 LiteralConstantEmitter &instType, 434 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS], 435 const CodeGenInstruction &inst) { 436 const std::string &name = inst.TheDef->getName(); 437 438 if (name.find("MOV") != name.npos) { 439 if (name.find("MOV_V") != name.npos) { 440 // ignore (this is a pseudoinstruction) 441 } else if (name.find("MASK") != name.npos) { 442 // ignore (this is a masking move) 443 } else if (name.find("r0") != name.npos) { 444 // ignore (this is a pseudoinstruction) 445 } else if (name.find("PS") != name.npos || 446 name.find("PD") != name.npos) { 447 // ignore (this is a shuffling move) 448 } else if (name.find("MOVS") != name.npos) { 449 // ignore (this is a string move) 450 } else if (name.find("_F") != name.npos) { 451 // TODO handle _F moves to ST(0) 452 } else if (name.find("a") != name.npos) { 453 // TODO handle moves to/from %ax 454 } else if (name.find("CMOV") != name.npos) { 455 MOV("src2", "dst"); 456 } else if (name.find("PC") != name.npos) { 457 MOV("label", "reg") 458 } else { 459 MOV("src", "dst"); 460 } 461 } 462 463 if (name.find("JMP") != name.npos || 464 name.find("J") == 0) { 465 if (name.find("FAR") != name.npos && name.find("i") != name.npos) { 466 BRANCH("off"); 467 } else { 468 BRANCH("dst"); 469 } 470 } 471 472 if (name.find("PUSH") != name.npos) { 473 if (name.find("CS") != name.npos || 474 name.find("DS") != name.npos || 475 name.find("ES") != name.npos || 476 name.find("FS") != name.npos || 477 name.find("GS") != name.npos || 478 name.find("SS") != name.npos) { 479 instType.set("kInstructionTypePush"); 480 // TODO add support for fixed operands 481 } else if (name.find("F") != name.npos) { 482 // ignore (this pushes onto the FP stack) 483 } else if (name.find("A") != name.npos) { 484 // ignore (pushes all GP registoers onto the stack) 485 } else if (name[name.length() - 1] == 'm') { 486 PUSH("src"); 487 } else if (name.find("i") != name.npos) { 488 PUSH("imm"); 489 } else { 490 PUSH("reg"); 491 } 492 } 493 494 if (name.find("POP") != name.npos) { 495 if (name.find("POPCNT") != name.npos) { 496 // ignore (not a real pop) 497 } else if (name.find("CS") != name.npos || 498 name.find("DS") != name.npos || 499 name.find("ES") != name.npos || 500 name.find("FS") != name.npos || 501 name.find("GS") != name.npos || 502 name.find("SS") != name.npos) { 503 instType.set("kInstructionTypePop"); 504 // TODO add support for fixed operands 505 } else if (name.find("F") != name.npos) { 506 // ignore (this pops from the FP stack) 507 } else if (name.find("A") != name.npos) { 508 // ignore (pushes all GP registoers onto the stack) 509 } else if (name[name.length() - 1] == 'm') { 510 POP("dst"); 511 } else { 512 POP("reg"); 513 } 514 } 515 516 if (name.find("CALL") != name.npos) { 517 if (name.find("ADJ") != name.npos) { 518 // ignore (not a call) 519 } else if (name.find("SYSCALL") != name.npos) { 520 // ignore (doesn't go anywhere we know about) 521 } else if (name.find("VMCALL") != name.npos) { 522 // ignore (rather different semantics than a regular call) 523 } else if (name.find("VMMCALL") != name.npos) { 524 // ignore (rather different semantics than a regular call) 525 } else if (name.find("FAR") != name.npos && name.find("i") != name.npos) { 526 CALL("off"); 527 } else { 528 CALL("dst"); 529 } 530 } 531 532 if (name.find("RET") != name.npos) { 533 RETURN(); 534 } 535 } 536 537 #undef MOV 538 #undef BRANCH 539 #undef PUSH 540 #undef POP 541 #undef CALL 542 #undef RETURN 543 544 ///////////////////////////////////////////////////// 545 // Support functions for handling ARM instructions // 546 ///////////////////////////////////////////////////// 547 548 #define SET(flag) { type->set(flag); return 0; } 549 550 #define REG(str) if (name == str) SET("kOperandTypeRegister"); 551 #define IMM(str) if (name == str) SET("kOperandTypeImmediate"); 552 553 #define MISC(str, type) if (name == str) SET(type); 554 555 /// ARMFlagFromOpName - Processes the name of a single ARM operand (which is 556 /// actually its type) and translates it into an operand type 557 /// 558 /// @arg type - The type object to set 559 /// @arg name - The name of the operand 560 static int ARMFlagFromOpName(LiteralConstantEmitter *type, 561 const std::string &name) { 562 REG("GPR"); 563 REG("rGPR"); 564 REG("GPRnopc"); 565 REG("GPRsp"); 566 REG("tcGPR"); 567 REG("cc_out"); 568 REG("s_cc_out"); 569 REG("tGPR"); 570 REG("DPR"); 571 REG("DPR_VFP2"); 572 REG("DPR_8"); 573 REG("DPair"); 574 REG("SPR"); 575 REG("QPR"); 576 REG("QQPR"); 577 REG("QQQQPR"); 578 REG("VecListOneD"); 579 REG("VecListDPair"); 580 REG("VecListDPairSpaced"); 581 REG("VecListThreeD"); 582 REG("VecListFourD"); 583 REG("VecListOneDAllLanes"); 584 REG("VecListDPairAllLanes"); 585 REG("VecListDPairSpacedAllLanes"); 586 587 IMM("i32imm"); 588 IMM("fbits16"); 589 IMM("fbits32"); 590 IMM("i32imm_hilo16"); 591 IMM("bf_inv_mask_imm"); 592 IMM("lsb_pos_imm"); 593 IMM("width_imm"); 594 IMM("jtblock_operand"); 595 IMM("nohash_imm"); 596 IMM("p_imm"); 597 IMM("pf_imm"); 598 IMM("c_imm"); 599 IMM("coproc_option_imm"); 600 IMM("imod_op"); 601 IMM("iflags_op"); 602 IMM("cpinst_operand"); 603 IMM("setend_op"); 604 IMM("cps_opt"); 605 IMM("vfp_f64imm"); 606 IMM("vfp_f32imm"); 607 IMM("memb_opt"); 608 IMM("msr_mask"); 609 IMM("neg_zero"); 610 IMM("imm0_31"); 611 IMM("imm0_31_m1"); 612 IMM("imm1_16"); 613 IMM("imm1_32"); 614 IMM("nModImm"); 615 IMM("nImmSplatI8"); 616 IMM("nImmSplatI16"); 617 IMM("nImmSplatI32"); 618 IMM("nImmSplatI64"); 619 IMM("nImmVMOVI32"); 620 IMM("nImmVMOVF32"); 621 IMM("imm8"); 622 IMM("imm16"); 623 IMM("imm32"); 624 IMM("imm1_7"); 625 IMM("imm1_15"); 626 IMM("imm1_31"); 627 IMM("imm0_1"); 628 IMM("imm0_3"); 629 IMM("imm0_7"); 630 IMM("imm0_15"); 631 IMM("imm0_255"); 632 IMM("imm0_4095"); 633 IMM("imm0_65535"); 634 IMM("imm0_65535_expr"); 635 IMM("imm24b"); 636 IMM("pkh_lsl_amt"); 637 IMM("pkh_asr_amt"); 638 IMM("jt2block_operand"); 639 IMM("t_imm0_1020s4"); 640 IMM("t_imm0_508s4"); 641 IMM("pclabel"); 642 IMM("adrlabel"); 643 IMM("t_adrlabel"); 644 IMM("t2adrlabel"); 645 IMM("shift_imm"); 646 IMM("t2_shift_imm"); 647 IMM("neon_vcvt_imm32"); 648 IMM("shr_imm8"); 649 IMM("shr_imm16"); 650 IMM("shr_imm32"); 651 IMM("shr_imm64"); 652 IMM("t2ldrlabel"); 653 IMM("postidx_imm8"); 654 IMM("postidx_imm8s4"); 655 IMM("imm_sr"); 656 IMM("imm1_31"); 657 IMM("VectorIndex8"); 658 IMM("VectorIndex16"); 659 IMM("VectorIndex32"); 660 661 MISC("brtarget", "kOperandTypeARMBranchTarget"); // ? 662 MISC("uncondbrtarget", "kOperandTypeARMBranchTarget"); // ? 663 MISC("t_brtarget", "kOperandTypeARMBranchTarget"); // ? 664 MISC("t_bcctarget", "kOperandTypeARMBranchTarget"); // ? 665 MISC("t_cbtarget", "kOperandTypeARMBranchTarget"); // ? 666 MISC("bltarget", "kOperandTypeARMBranchTarget"); // ? 667 668 MISC("br_target", "kOperandTypeARMBranchTarget"); // ? 669 MISC("bl_target", "kOperandTypeARMBranchTarget"); // ? 670 MISC("blx_target", "kOperandTypeARMBranchTarget"); // ? 671 672 MISC("t_bltarget", "kOperandTypeARMBranchTarget"); // ? 673 MISC("t_blxtarget", "kOperandTypeARMBranchTarget"); // ? 674 MISC("so_reg_imm", "kOperandTypeARMSoRegReg"); // R, R, I 675 MISC("so_reg_reg", "kOperandTypeARMSoRegImm"); // R, R, I 676 MISC("shift_so_reg_reg", "kOperandTypeARMSoRegReg"); // R, R, I 677 MISC("shift_so_reg_imm", "kOperandTypeARMSoRegImm"); // R, R, I 678 MISC("t2_so_reg", "kOperandTypeThumb2SoReg"); // R, I 679 MISC("so_imm", "kOperandTypeARMSoImm"); // I 680 MISC("rot_imm", "kOperandTypeARMRotImm"); // I 681 MISC("t2_so_imm", "kOperandTypeThumb2SoImm"); // I 682 MISC("so_imm2part", "kOperandTypeARMSoImm2Part"); // I 683 MISC("pred", "kOperandTypeARMPredicate"); // I, R 684 MISC("it_pred", "kOperandTypeARMPredicate"); // I 685 MISC("addrmode_imm12", "kOperandTypeAddrModeImm12"); // R, I 686 MISC("ldst_so_reg", "kOperandTypeLdStSOReg"); // R, R, I 687 MISC("postidx_reg", "kOperandTypeARMAddrMode3Offset"); // R, I 688 MISC("addrmode2", "kOperandTypeARMAddrMode2"); // R, R, I 689 MISC("am2offset_reg", "kOperandTypeARMAddrMode2Offset"); // R, I 690 MISC("am2offset_imm", "kOperandTypeARMAddrMode2Offset"); // R, I 691 MISC("addrmode3", "kOperandTypeARMAddrMode3"); // R, R, I 692 MISC("am3offset", "kOperandTypeARMAddrMode3Offset"); // R, I 693 MISC("ldstm_mode", "kOperandTypeARMLdStmMode"); // I 694 MISC("addrmode5", "kOperandTypeARMAddrMode5"); // R, I 695 MISC("addrmode6", "kOperandTypeARMAddrMode6"); // R, R, I, I 696 MISC("am6offset", "kOperandTypeARMAddrMode6Offset"); // R, I, I 697 MISC("addrmode6dup", "kOperandTypeARMAddrMode6"); // R, R, I, I 698 MISC("addrmode6oneL32", "kOperandTypeARMAddrMode6"); // R, R, I, I 699 MISC("addrmodepc", "kOperandTypeARMAddrModePC"); // R, I 700 MISC("addr_offset_none", "kOperandTypeARMAddrMode7"); // R 701 MISC("reglist", "kOperandTypeARMRegisterList"); // I, R, ... 702 MISC("dpr_reglist", "kOperandTypeARMDPRRegisterList"); // I, R, ... 703 MISC("spr_reglist", "kOperandTypeARMSPRRegisterList"); // I, R, ... 704 MISC("it_mask", "kOperandTypeThumbITMask"); // I 705 MISC("t2addrmode_reg", "kOperandTypeThumb2AddrModeReg"); // R 706 MISC("t2addrmode_posimm8", "kOperandTypeThumb2AddrModeImm8"); // R, I 707 MISC("t2addrmode_negimm8", "kOperandTypeThumb2AddrModeImm8"); // R, I 708 MISC("t2addrmode_imm8", "kOperandTypeThumb2AddrModeImm8"); // R, I 709 MISC("t2am_imm8_offset", "kOperandTypeThumb2AddrModeImm8Offset");//I 710 MISC("t2addrmode_imm12", "kOperandTypeThumb2AddrModeImm12"); // R, I 711 MISC("t2addrmode_so_reg", "kOperandTypeThumb2AddrModeSoReg"); // R, R, I 712 MISC("t2addrmode_imm8s4", "kOperandTypeThumb2AddrModeImm8s4"); // R, I 713 MISC("t2addrmode_imm0_1020s4", "kOperandTypeThumb2AddrModeImm8s4"); // R, I 714 MISC("t2am_imm8s4_offset", "kOperandTypeThumb2AddrModeImm8s4Offset"); 715 // R, I 716 MISC("tb_addrmode", "kOperandTypeARMTBAddrMode"); // I 717 MISC("t_addrmode_rrs1", "kOperandTypeThumbAddrModeRegS1"); // R, R 718 MISC("t_addrmode_rrs2", "kOperandTypeThumbAddrModeRegS2"); // R, R 719 MISC("t_addrmode_rrs4", "kOperandTypeThumbAddrModeRegS4"); // R, R 720 MISC("t_addrmode_is1", "kOperandTypeThumbAddrModeImmS1"); // R, I 721 MISC("t_addrmode_is2", "kOperandTypeThumbAddrModeImmS2"); // R, I 722 MISC("t_addrmode_is4", "kOperandTypeThumbAddrModeImmS4"); // R, I 723 MISC("t_addrmode_rr", "kOperandTypeThumbAddrModeRR"); // R, R 724 MISC("t_addrmode_sp", "kOperandTypeThumbAddrModeSP"); // R, I 725 MISC("t_addrmode_pc", "kOperandTypeThumbAddrModePC"); // R, I 726 MISC("addrmode_tbb", "kOperandTypeThumbAddrModeRR"); // R, R 727 MISC("addrmode_tbh", "kOperandTypeThumbAddrModeRR"); // R, R 728 729 return 1; 730 } 731 732 #undef REG 733 #undef MEM 734 #undef MISC 735 736 #undef SET 737 738 /// ARMPopulateOperands - Handles all the operands in an ARM instruction, adding 739 /// the appropriate flags to their descriptors 740 /// 741 /// @operandFlags - A reference the array of operand flag objects 742 /// @inst - The instruction to use as a source of information 743 static void ARMPopulateOperands( 744 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS], 745 const CodeGenInstruction &inst) { 746 if (!inst.TheDef->isSubClassOf("InstARM") && 747 !inst.TheDef->isSubClassOf("InstThumb")) 748 return; 749 750 unsigned int index; 751 unsigned int numOperands = inst.Operands.size(); 752 753 if (numOperands > EDIS_MAX_OPERANDS) { 754 errs() << "numOperands == " << numOperands << " > " << 755 EDIS_MAX_OPERANDS << '\n'; 756 llvm_unreachable("Too many operands"); 757 } 758 759 for (index = 0; index < numOperands; ++index) { 760 const CGIOperandList::OperandInfo &operandInfo = inst.Operands[index]; 761 Record &rec = *operandInfo.Rec; 762 763 if (ARMFlagFromOpName(operandTypes[index], rec.getName())) { 764 errs() << "Operand type: " << rec.getName() << '\n'; 765 errs() << "Operand name: " << operandInfo.Name << '\n'; 766 errs() << "Instruction name: " << inst.TheDef->getName() << '\n'; 767 throw("Unhandled type in EDEmitter"); 768 } 769 } 770 } 771 772 #define BRANCH(target) { \ 773 instType.set("kInstructionTypeBranch"); \ 774 DECORATE1(target, "kOperandFlagTarget"); \ 775 } 776 777 /// ARMExtractSemantics - Performs various checks on the name of an ARM 778 /// instruction to determine what sort of an instruction it is and then adds 779 /// the appropriate flags to the instruction and its operands 780 /// 781 /// @arg instType - A reference to the type for the instruction as a whole 782 /// @arg operandTypes - A reference to the array of operand type object pointers 783 /// @arg operandFlags - A reference to the array of operand flag object pointers 784 /// @arg inst - A reference to the original instruction 785 static void ARMExtractSemantics( 786 LiteralConstantEmitter &instType, 787 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS], 788 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS], 789 const CodeGenInstruction &inst) { 790 const std::string &name = inst.TheDef->getName(); 791 792 if (name == "tBcc" || 793 name == "tB" || 794 name == "t2Bcc" || 795 name == "Bcc" || 796 name == "tCBZ" || 797 name == "tCBNZ") { 798 BRANCH("target"); 799 } 800 801 if (name == "tBLr9" || 802 name == "BLr9_pred" || 803 name == "tBLXi_r9" || 804 name == "tBLXr_r9" || 805 name == "BLXr9" || 806 name == "t2BXJ" || 807 name == "BXJ") { 808 BRANCH("func"); 809 810 unsigned opIndex; 811 opIndex = inst.Operands.getOperandNamed("func"); 812 if (operandTypes[opIndex]->is("kOperandTypeImmediate")) 813 operandTypes[opIndex]->set("kOperandTypeARMBranchTarget"); 814 } 815 } 816 817 #undef BRANCH 818 819 /// populateInstInfo - Fills an array of InstInfos with information about each 820 /// instruction in a target 821 /// 822 /// @arg infoArray - The array of InstInfo objects to populate 823 /// @arg target - The CodeGenTarget to use as a source of instructions 824 static void populateInstInfo(CompoundConstantEmitter &infoArray, 825 CodeGenTarget &target) { 826 const std::vector<const CodeGenInstruction*> &numberedInstructions = 827 target.getInstructionsByEnumValue(); 828 829 unsigned int index; 830 unsigned int numInstructions = numberedInstructions.size(); 831 832 for (index = 0; index < numInstructions; ++index) { 833 const CodeGenInstruction& inst = *numberedInstructions[index]; 834 835 CompoundConstantEmitter *infoStruct = new CompoundConstantEmitter; 836 infoArray.addEntry(infoStruct); 837 838 LiteralConstantEmitter *instType = new LiteralConstantEmitter; 839 infoStruct->addEntry(instType); 840 841 LiteralConstantEmitter *numOperandsEmitter = 842 new LiteralConstantEmitter(inst.Operands.size()); 843 infoStruct->addEntry(numOperandsEmitter); 844 845 CompoundConstantEmitter *operandTypeArray = new CompoundConstantEmitter; 846 infoStruct->addEntry(operandTypeArray); 847 848 LiteralConstantEmitter *operandTypes[EDIS_MAX_OPERANDS]; 849 850 CompoundConstantEmitter *operandFlagArray = new CompoundConstantEmitter; 851 infoStruct->addEntry(operandFlagArray); 852 853 FlagsConstantEmitter *operandFlags[EDIS_MAX_OPERANDS]; 854 855 for (unsigned operandIndex = 0; 856 operandIndex < EDIS_MAX_OPERANDS; 857 ++operandIndex) { 858 operandTypes[operandIndex] = new LiteralConstantEmitter; 859 operandTypeArray->addEntry(operandTypes[operandIndex]); 860 861 operandFlags[operandIndex] = new FlagsConstantEmitter; 862 operandFlagArray->addEntry(operandFlags[operandIndex]); 863 } 864 865 unsigned numSyntaxes = 0; 866 867 // We don't need to do anything for pseudo-instructions, as we'll never 868 // see them here. We'll only see real instructions. 869 // We still need to emit null initializers for everything. 870 if (!inst.isPseudo) { 871 if (target.getName() == "X86") { 872 X86PopulateOperands(operandTypes, inst); 873 X86ExtractSemantics(*instType, operandFlags, inst); 874 numSyntaxes = 2; 875 } 876 else if (target.getName() == "ARM") { 877 ARMPopulateOperands(operandTypes, inst); 878 ARMExtractSemantics(*instType, operandTypes, operandFlags, inst); 879 numSyntaxes = 1; 880 } 881 } 882 883 CompoundConstantEmitter *operandOrderArray = new CompoundConstantEmitter; 884 885 infoStruct->addEntry(operandOrderArray); 886 887 for (unsigned syntaxIndex = 0; 888 syntaxIndex < EDIS_MAX_SYNTAXES; 889 ++syntaxIndex) { 890 CompoundConstantEmitter *operandOrder = 891 new CompoundConstantEmitter(EDIS_MAX_OPERANDS); 892 893 operandOrderArray->addEntry(operandOrder); 894 895 if (syntaxIndex < numSyntaxes) { 896 populateOperandOrder(operandOrder, inst, syntaxIndex); 897 } 898 } 899 900 infoStruct = NULL; 901 } 902 } 903 904 static void emitCommonEnums(raw_ostream &o, unsigned int &i) { 905 EnumEmitter operandTypes("OperandTypes"); 906 operandTypes.addEntry("kOperandTypeNone"); 907 operandTypes.addEntry("kOperandTypeImmediate"); 908 operandTypes.addEntry("kOperandTypeRegister"); 909 operandTypes.addEntry("kOperandTypeX86Memory"); 910 operandTypes.addEntry("kOperandTypeX86EffectiveAddress"); 911 operandTypes.addEntry("kOperandTypeX86PCRelative"); 912 operandTypes.addEntry("kOperandTypeARMBranchTarget"); 913 operandTypes.addEntry("kOperandTypeARMSoRegReg"); 914 operandTypes.addEntry("kOperandTypeARMSoRegImm"); 915 operandTypes.addEntry("kOperandTypeARMSoImm"); 916 operandTypes.addEntry("kOperandTypeARMRotImm"); 917 operandTypes.addEntry("kOperandTypeARMSoImm2Part"); 918 operandTypes.addEntry("kOperandTypeARMPredicate"); 919 operandTypes.addEntry("kOperandTypeAddrModeImm12"); 920 operandTypes.addEntry("kOperandTypeLdStSOReg"); 921 operandTypes.addEntry("kOperandTypeARMAddrMode2"); 922 operandTypes.addEntry("kOperandTypeARMAddrMode2Offset"); 923 operandTypes.addEntry("kOperandTypeARMAddrMode3"); 924 operandTypes.addEntry("kOperandTypeARMAddrMode3Offset"); 925 operandTypes.addEntry("kOperandTypeARMLdStmMode"); 926 operandTypes.addEntry("kOperandTypeARMAddrMode5"); 927 operandTypes.addEntry("kOperandTypeARMAddrMode6"); 928 operandTypes.addEntry("kOperandTypeARMAddrMode6Offset"); 929 operandTypes.addEntry("kOperandTypeARMAddrMode7"); 930 operandTypes.addEntry("kOperandTypeARMAddrModePC"); 931 operandTypes.addEntry("kOperandTypeARMRegisterList"); 932 operandTypes.addEntry("kOperandTypeARMDPRRegisterList"); 933 operandTypes.addEntry("kOperandTypeARMSPRRegisterList"); 934 operandTypes.addEntry("kOperandTypeARMTBAddrMode"); 935 operandTypes.addEntry("kOperandTypeThumbITMask"); 936 operandTypes.addEntry("kOperandTypeThumbAddrModeImmS1"); 937 operandTypes.addEntry("kOperandTypeThumbAddrModeImmS2"); 938 operandTypes.addEntry("kOperandTypeThumbAddrModeImmS4"); 939 operandTypes.addEntry("kOperandTypeThumbAddrModeRegS1"); 940 operandTypes.addEntry("kOperandTypeThumbAddrModeRegS2"); 941 operandTypes.addEntry("kOperandTypeThumbAddrModeRegS4"); 942 operandTypes.addEntry("kOperandTypeThumbAddrModeRR"); 943 operandTypes.addEntry("kOperandTypeThumbAddrModeSP"); 944 operandTypes.addEntry("kOperandTypeThumbAddrModePC"); 945 operandTypes.addEntry("kOperandTypeThumb2AddrModeReg"); 946 operandTypes.addEntry("kOperandTypeThumb2SoReg"); 947 operandTypes.addEntry("kOperandTypeThumb2SoImm"); 948 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8"); 949 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8Offset"); 950 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm12"); 951 operandTypes.addEntry("kOperandTypeThumb2AddrModeSoReg"); 952 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4"); 953 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4Offset"); 954 operandTypes.emit(o, i); 955 956 o << "\n"; 957 958 EnumEmitter operandFlags("OperandFlags"); 959 operandFlags.addEntry("kOperandFlagSource"); 960 operandFlags.addEntry("kOperandFlagTarget"); 961 operandFlags.emitAsFlags(o, i); 962 963 o << "\n"; 964 965 EnumEmitter instructionTypes("InstructionTypes"); 966 instructionTypes.addEntry("kInstructionTypeNone"); 967 instructionTypes.addEntry("kInstructionTypeMove"); 968 instructionTypes.addEntry("kInstructionTypeBranch"); 969 instructionTypes.addEntry("kInstructionTypePush"); 970 instructionTypes.addEntry("kInstructionTypePop"); 971 instructionTypes.addEntry("kInstructionTypeCall"); 972 instructionTypes.addEntry("kInstructionTypeReturn"); 973 instructionTypes.emit(o, i); 974 975 o << "\n"; 976 } 977 978 void EDEmitter::run(raw_ostream &o) { 979 unsigned int i = 0; 980 981 CompoundConstantEmitter infoArray; 982 CodeGenTarget target(Records); 983 984 populateInstInfo(infoArray, target); 985 986 emitCommonEnums(o, i); 987 988 o << "static const llvm::EDInstInfo instInfo" << target.getName() << "[] = "; 989 infoArray.emit(o, i); 990 o << ";" << "\n"; 991 } 992
