1 /* -*- mode: C; c-basic-offset: 3; -*- */ 2 3 /*--------------------------------------------------------------------*/ 4 /*--- s390x-specific definitions. cg-s390x.c ---*/ 5 /*--------------------------------------------------------------------*/ 6 7 /* 8 This file is part of Cachegrind, a Valgrind tool for cache 9 profiling programs. 10 11 Copyright IBM Corp. 2010-2011 12 13 This program is free software; you can redistribute it and/or 14 modify it under the terms of the GNU General Public License as 15 published by the Free Software Foundation; either version 2 of the 16 License, or (at your option) any later version. 17 18 This program is distributed in the hope that it will be useful, but 19 WITHOUT ANY WARRANTY; without even the implied warranty of 20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 21 General Public License for more details. 22 23 You should have received a copy of the GNU General Public License 24 along with this program; if not, write to the Free Software 25 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 26 02111-1307, USA. 27 28 The GNU General Public License is contained in the file COPYING. 29 */ 30 31 /* Contributed by Christian Borntraeger */ 32 33 #if defined(VGA_s390x) 34 35 #include "pub_tool_basics.h" 36 #include "pub_tool_libcbase.h" 37 #include "pub_tool_libcassert.h" 38 #include "pub_tool_libcprint.h" 39 40 #include "cg_arch.h" 41 42 void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* L2c, 43 Bool all_caches_clo_defined) 44 { 45 // z900 46 // 47 // Source: 48 // The microarchitecture of the IBM eServer z900 processor 49 // IBM Journal of Research and Development 50 // Volume 46, Number 4/5, pp 381-395, July/September 2002 51 // 52 // Split L1 I/D cache 53 // Size: 256 kB each 54 // Line size: 256 bytes 55 // 4-way set associative 56 // L2 cache: 16 MB x 2 (16 MB per 10 CPs) (Charles Webb) 57 58 // z800 59 // 60 // Source: Charles Webb from IBM 61 // 62 // Split L1 I/D cache 63 // Size: 256 kB each 64 // Line size: 256 bytes 65 // 4-way set associative 66 // L2 cache: 16 MB (or half that size) 67 68 // z990 69 // 70 // The IBM eServer z990 microprocessor 71 // IBM Journal of Research and Development 72 // Volume 48, Number 3/4, pp 295-309, May/July 2004 73 // 74 // Split L1 I/D cache 75 // Size: 256 kB each 76 // Line size: 256 bytes 77 // 4-way set associative 78 // L2 cache: 32 MB x 4 (32 MB per book/node) (Charles Webb) 79 80 // z890 81 // 82 // Source: Charles Webb from IBM 83 // 84 // Split L1 I/D cache 85 // Size: 256 kB each 86 // Line size: 256 bytes 87 // 4-way set associative 88 // L2 cache: 32 MB (or half that size) 89 90 // z9 91 // 92 // Source: Charles Webb from IBM 93 // 94 // Split L1 I/D cache 95 // Size: 256 kB each 96 // Line size: 256 bytes 97 // 4-way set associative 98 // L2 cache: 40 MB x 4 (40 MB per book/node) 99 100 101 // Set caches to z10 default. 102 // See IBM Journal of Research and Development 103 // Issue Date: Jan. 2009 104 // Volume: 53 Issue:1 105 // fixs390: have a table for all available models and check /proc/cpuinfo 106 *I1c = (cache_t) { 65536, 4, 256 }; 107 *D1c = (cache_t) { 131072, 8, 256 }; 108 *L2c = (cache_t) { 3145728, 12, 256 }; 109 110 // Warn if config not completely specified from cmd line. Note that 111 // this message is slightly different from the one we give on x86/AMD64 112 // when auto-detection fails; this lets us filter out this one (which is 113 // not important) in the regression test suite without filtering the 114 // x86/AMD64 one (which we want to see if it ever occurs in the 115 // regression test suite). 116 // 117 // If you change this message, please update 118 // cachegrind/tests/filter_stderr! 119 // 120 if (!all_caches_clo_defined) { 121 VG_(dmsg)("Warning: Cannot auto-detect cache config on s390x, using one " 122 "or more defaults \n"); 123 } 124 } 125 126 #endif 127 128 /*--------------------------------------------------------------------*/ 129 /*--- end cg-s390x.c ---*/ 130 /*--------------------------------------------------------------------*/ 131
