Lines Matching defs:Opcode
54 uint16_t MLxOpc; // MLA / MLS opcode
55 uint16_t MulOpc; // Expanded multiplication opcode
56 uint16_t AddSubOpc; // Expanded add / sub opcode
1140 // Change the opcode and operands.
1224 unsigned Opcode = Orig->getOpcode();
1225 switch (Opcode) {
1237 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1265 int Opcode = MI0->getOpcode();
1266 if (Opcode == ARM::t2LDRpci ||
1267 Opcode == ARM::t2LDRpci_pic ||
1268 Opcode == ARM::tLDRpci ||
1269 Opcode == ARM::tLDRpci_pic ||
1270 Opcode == ARM::MOV_ga_dyn ||
1271 Opcode == ARM::MOV_ga_pcrel ||
1272 Opcode == ARM::MOV_ga_pcrel_ldr ||
1273 Opcode == ARM::t2MOV_ga_dyn ||
1274 Opcode == ARM::t2MOV_ga_pcrel) {
1275 if (MI1->getOpcode() != Opcode)
1285 if (Opcode == ARM::MOV_ga_dyn ||
1286 Opcode == ARM::MOV_ga_pcrel ||
1287 Opcode == ARM::MOV_ga_pcrel_ldr ||
1288 Opcode == ARM::t2MOV_ga_dyn ||
1289 Opcode == ARM::t2MOV_ga_pcrel)
1311 } else if (Opcode == ARM::PICLDR) {
1312 if (MI1->getOpcode() != Opcode)
1555 llvm_unreachable("Unknown unconditional branch opcode!");
1766 unsigned Opcode = MI.getOpcode();
1772 if (Opcode == ARM::INLINEASM)
1775 if (Opcode == ARM::ADDri) {
1863 // Attempt to fold address comp. if opcode has offset bits
2761 /// itinerary based on the def opcode and alignment. The caller will ensure that
2992 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3010 if (isZeroCost(DefMCID.Opcode))
3240 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3258 unsigned Opcode = Node->getMachineOpcode();
3259 switch (Opcode) {
3261 return ItinData->getStageLatency(get(Opcode).getSchedClass());
3316 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
3319 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
3406 llvm_unreachable("cannot handle opcode!");
