Lines Matching refs:DefIdx
2454 unsigned DefIdx, unsigned DefAlign) const {
2455 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2458 return ItinData->getOperandCycle(DefClass, DefIdx);
2495 unsigned DefIdx, unsigned DefAlign) const {
2496 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2499 return ItinData->getOperandCycle(DefClass, DefIdx);
2598 unsigned DefIdx, unsigned DefAlign,
2604 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
2605 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
2614 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2623 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2644 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2693 // It's a variable_ops instruction so we can't use DefIdx here. Just use
2698 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
2709 unsigned &DefIdx, unsigned &Dist) {
2727 DefIdx = Idx;
2914 const MachineInstr *DefMI, unsigned DefIdx,
2921 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
2928 DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj);
2983 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign,
3003 SDNode *DefNode, unsigned DefIdx,
3017 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
3031 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
3190 const MachineInstr *DefMI, unsigned DefIdx,
3192 unsigned Reg = DefMI->getOperand(DefIdx).getReg();
3271 const MachineInstr *DefMI, unsigned DefIdx,
3281 int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx,
3293 const MachineInstr *DefMI, unsigned DefIdx) const {
3300 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
