Lines Matching refs:MI
51 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
53 unsigned Opcode = MI->getOpcode();
57 switch (MI->getOperand(0).getImm()) {
65 printInstruction(MI, O);
69 printPredicateOperand(MI, 1, O);
79 const MCOperand &Dst = MI->getOperand(0);
80 const MCOperand &MO1 = MI->getOperand(1);
81 const MCOperand &MO2 = MI->getOperand(2);
82 const MCOperand &MO3 = MI->getOperand(3);
85 printSBitModifierOperand(MI, 6, O);
86 printPredicateOperand(MI, 4, O);
99 const MCOperand &Dst = MI->getOperand(0);
100 const MCOperand &MO1 = MI->getOperand(1);
101 const MCOperand &MO2 = MI->getOperand(2);
104 printSBitModifierOperand(MI, 5, O);
105 printPredicateOperand(MI, 3, O);
123 MI->getOperand(0).getReg() == ARM::SP &&
124 MI->getNumOperands() > 5) {
127 printPredicateOperand(MI, 2, O);
131 printRegisterList(MI, 4, O);
135 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
136 MI->getOperand(3).getImm() == -4) {
138 printPredicateOperand(MI, 4, O);
139 O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
146 MI->getOperand(0).getReg() == ARM::SP &&
147 MI->getNumOperands() > 5) {
150 printPredicateOperand(MI, 2, O);
154 printRegisterList(MI, 4, O);
158 if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
159 MI->getOperand(4).getImm() == 4) {
161 printPredicateOperand(MI, 5, O);
162 O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}";
170 MI->getOperand(0).getReg() == ARM::SP) {
172 printPredicateOperand(MI, 2, O);
174 printRegisterList(MI, 4, O);
181 MI->getOperand(0).getReg() == ARM::SP) {
183 printPredicateOperand(MI, 2, O);
185 printRegisterList(MI, 4, O);
192 unsigned BaseReg = MI->getOperand(0).getReg();
193 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
194 if (MI->getOperand(i).getReg() == BaseReg)
200 printPredicateOperand(MI, 1, O);
204 printRegisterList(MI, 3, O);
210 if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 &&
211 MI->getOperand(1).getReg() == ARM::R8) {
213 printPredicateOperand(MI, 2, O);
218 printInstruction(MI, O);
222 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
224 const MCOperand &Op = MI->getOperand(OpNo);
247 void ARMInstPrinter::printT2LdrLabelOperand(const MCInst *MI, unsigned OpNum,
249 const MCOperand &MO1 = MI->getOperand(OpNum);
263 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
265 const MCOperand &MO1 = MI->getOperand(OpNum);
266 const MCOperand &MO2 = MI->getOperand(OpNum+1);
267 const MCOperand &MO3 = MI->getOperand(OpNum+2);
281 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
283 const MCOperand &MO1 = MI->getOperand(OpNum);
284 const MCOperand &MO2 = MI->getOperand(OpNum+1);
301 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
303 const MCOperand &MO1 = MI->getOperand(Op);
304 const MCOperand &MO2 = MI->getOperand(Op+1);
305 const MCOperand &MO3 = MI->getOperand(Op+2);
329 void ARMInstPrinter::printAM2PostIndexOp(const MCInst *MI, unsigned Op,
331 const MCOperand &MO1 = MI->getOperand(Op);
332 const MCOperand &MO2 = MI->getOperand(Op+1);
333 const MCOperand &MO3 = MI->getOperand(Op+2);
354 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
356 const MCOperand &MO1 = MI->getOperand(Op);
357 const MCOperand &MO2 = MI->getOperand(Op+1);
362 void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
364 const MCOperand &MO1 = MI->getOperand(Op);
365 const MCOperand &MO2 = MI->getOperand(Op+1);
370 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
372 const MCOperand &MO1 = MI->getOperand(Op);
375 printOperand(MI, Op, O);
379 const MCOperand &MO3 = MI->getOperand(Op+2);
383 printAM2PostIndexOp(MI, Op, O);
386 printAM2PreOrOffsetIndexOp(MI, Op, O);
389 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
392 const MCOperand &MO1 = MI->getOperand(OpNum);
393 const MCOperand &MO2 = MI->getOperand(OpNum+1);
416 void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op,
418 const MCOperand &MO1 = MI->getOperand(Op);
419 const MCOperand &MO2 = MI->getOperand(Op+1);
420 const MCOperand &MO3 = MI->getOperand(Op+2);
436 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
438 const MCOperand &MO1 = MI->getOperand(Op);
439 const MCOperand &MO2 = MI->getOperand(Op+1);
440 const MCOperand &MO3 = MI->getOperand(Op+2);
461 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
463 const MCOperand &MO1 = MI->getOperand(Op);
465 printOperand(MI, Op, O);
469 const MCOperand &MO3 = MI->getOperand(Op+2);
473 printAM3PostIndexOp(MI, Op, O);
476 printAM3PreOrOffsetIndexOp(MI, Op, O);
479 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
482 const MCOperand &MO1 = MI->getOperand(OpNum);
483 const MCOperand &MO2 = MI->getOperand(OpNum+1);
497 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
500 const MCOperand &MO = MI->getOperand(OpNum);
505 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
507 const MCOperand &MO1 = MI->getOperand(OpNum);
508 const MCOperand &MO2 = MI->getOperand(OpNum+1);
513 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
516 const MCOperand &MO = MI->getOperand(OpNum);
522 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
524 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
529 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
531 const MCOperand &MO1 = MI->getOperand(OpNum);
532 const MCOperand &MO2 = MI->getOperand(OpNum+1);
535 printOperand(MI, OpNum, O);
551 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
553 const MCOperand &MO1 = MI->getOperand(OpNum);
554 const MCOperand &MO2 = MI->getOperand(OpNum+1);
564 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
566 const MCOperand &MO1 = MI->getOperand(OpNum);
570 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
573 const MCOperand &MO = MI->getOperand(OpNum);
580 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
583 const MCOperand &MO = MI->getOperand(OpNum);
591 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
593 unsigned val = MI->getOperand(OpNum).getImm();
597 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
599 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
608 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
610 unsigned Imm = MI->getOperand(OpNum).getImm();
617 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
619 unsigned Imm = MI->getOperand(OpNum).getImm();
627 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
630 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
632 O << getRegisterName(MI->getOperand(i).getReg());
637 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
639 const MCOperand &Op = MI->getOperand(OpNum);
646 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
648 const MCOperand &Op = MI->getOperand(OpNum);
652 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
654 const MCOperand &Op = MI->getOperand(OpNum);
664 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
666 const MCOperand &Op = MI->getOperand(OpNum);
672 unsigned Opcode = MI->getOpcode();
744 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
746 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
754 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
757 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
761 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
763 if (MI->getOperand(OpNum).getReg()) {
764 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
770 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
772 O << MI->getOperand(OpNum).getImm();
775 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
777 O << "p" << MI->getOperand(OpNum).getImm();
780 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
782 O << "c" << MI->getOperand(OpNum).getImm();
785 void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
787 O << "{" << MI->getOperand(OpNum).getImm() << "}";
790 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
795 void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
797 const MCOperand &MO = MI->getOperand(OpNum);
814 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
816 O << "#" << MI->getOperand(OpNum).getImm() * 4;
819 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
821 unsigned Imm = MI->getOperand(OpNum).getImm();
825 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
828 unsigned Mask = MI->getOperand(OpNum).getImm();
829 unsigned Firstcond = MI->getOperand(OpNum-1).getImm();
842 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
844 const MCOperand &MO1 = MI->getOperand(Op);
845 const MCOperand &MO2 = MI->getOperand(Op + 1);
848 printOperand(MI, Op, O);
858 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
862 const MCOperand &MO1 = MI->getOperand(Op);
863 const MCOperand &MO2 = MI->getOperand(Op + 1);
866 printOperand(MI, Op, O);
876 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
879 printThumbAddrModeImm5SOperand(MI, Op, O, 1);
882 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
885 printThumbAddrModeImm5SOperand(MI, Op, O, 2);
888 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
891 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
894 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
896 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
903 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
905 const MCOperand &MO1 = MI->getOperand(OpNum);
906 const MCOperand &MO2 = MI->getOperand(OpNum+1);
919 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
921 const MCOperand &MO1 = MI->getOperand(OpNum);
922 const MCOperand &MO2 = MI->getOperand(OpNum+1);
925 printOperand(MI, OpNum, O);
943 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
946 const MCOperand &MO1 = MI->getOperand(OpNum);
947 const MCOperand &MO2 = MI->getOperand(OpNum+1);
962 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
965 const MCOperand &MO1 = MI->getOperand(OpNum);
966 const MCOperand &MO2 = MI->getOperand(OpNum+1);
969 printOperand(MI, OpNum, O);
989 void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI,
992 const MCOperand &MO1 = MI->getOperand(OpNum);
993 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1001 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
1004 const MCOperand &MO1 = MI->getOperand(OpNum);
1013 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
1016 const MCOperand &MO1 = MI->getOperand(OpNum);
1030 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
1033 const MCOperand &MO1 = MI->getOperand(OpNum);
1034 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1035 const MCOperand &MO3 = MI->getOperand(OpNum+2);
1050 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1052 const MCOperand &MO = MI->getOperand(OpNum);
1056 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
1058 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1065 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
1067 unsigned Imm = MI->getOperand(OpNum).getImm();
1071 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
1073 unsigned Imm = MI->getOperand(OpNum).getImm();
1085 void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1087 O << "#" << 16 - MI->getOperand(OpNum).getImm();
1090 void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1092 O << "#" << 32 - MI->getOperand(OpNum).getImm();
1095 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1097 O << "[" << MI->getOperand(OpNum).getImm() << "]";
1100 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1102 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "}";
1105 void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1107 unsigned Reg = MI->getOperand(OpNum).getReg();
1113 void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI,
1116 unsigned Reg = MI->getOperand(OpNum).getReg();
1122 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1127 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1128 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << ", "
1129 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "}";
1132 void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1137 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1138 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << ", "
1139 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
1140 << getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "}";
1143 void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
1146 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[]}";
1149 void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
1152 unsigned Reg = MI->getOperand(OpNum).getReg();
1158 void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
1164 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1165 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[], "
1166 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[]}";
1169 void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
1175 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1176 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[], "
1177 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], "
1178 << getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "[]}";
1181 void ARMInstPrinter::printVectorListTwoSpacedAllLanes(const MCInst *MI,
1184 unsigned Reg = MI->getOperand(OpNum).getReg();
1190 void ARMInstPrinter::printVectorListThreeSpacedAllLanes(const MCInst *MI,
1196 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1197 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], "
1198 << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "[]}";
1201 void ARMInstPrinter::printVectorListFourSpacedAllLanes(const MCInst *MI,
1207 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1208 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], "
1209 << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "[], "
1210 << getRegisterName(MI->getOperand(OpNum).getReg() + 6) << "[]}";
1213 void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
1219 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1220 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
1221 << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "}";
1224 void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI,
1230 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1231 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
1232 << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << ", "
1233 << getRegisterName(MI->getOperand(OpNum).getReg() + 6) << "}";
