Lines Matching refs:VA
727 CCValAssign &VA = ArgLocs[i];
728 MVT RegVT = VA.getLocVT();
732 switch (VA.getLocInfo()) {
748 if (VA.isRegLoc()) {
749 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
752 assert(VA.isMemLoc());
760 unsigned ArgSize = VA.getValVT().getSizeInBits()/8;
761 unsigned StackLoc = VA.getLocMemOffset() + 4;
899 CCValAssign &VA = ArgLocs[i];
902 if (VA.isRegLoc()) {
903 MVT RegVT = VA.getLocVT();
904 ArgRegEnd = VA.getLocReg();
923 if (VA.getLocInfo() != CCValAssign::Full) {
925 if (VA.getLocInfo() == CCValAssign::SExt)
927 else if (VA.getLocInfo() == CCValAssign::ZExt)
931 DAG.getValueType(VA.getValVT()));
932 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
936 } else { // VA.isRegLoc()
938 assert(VA.isMemLoc());
951 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
952 unsigned StackLoc = VA.getLocMemOffset() + 4;
959 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1042 CCValAssign &VA = RVLocs[i];
1043 assert(VA.isRegLoc() && "Can only return in registers!");
1045 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
