Lines Matching full:v4i8
49 // Extract v4i8
54 (v4i8 V4I8Regs:$src), imm:$c))],
116 // Insert v4i8
274 def V4I8 : VecBinaryOp<V4AsmStr<!strconcat(asmstr, "16")>, OpNode, V4I8Regs,
308 def V4I8 : VecUnaryOp<V4UnaryStr<!strconcat(asmstr, "16")>, OpNode,
794 def : Pat<(v4i8 (vec_shuf:$op V4I8Regs:$src1, V4I8Regs:$src2)),
1007 def V4I8 : Vec_Compare<op, V4I8Regs, V4I8Regs, inst8>;
1255 // v4i8 -> i32
1279 // i32 -> v4i8
1307 // v4i8 -> v2i16
1317 // v2i16 -> v4i8
1318 def : Pat<(v4i8 (bitconvert V2I16Regs:$s)),
1353 // f32 -> v4i8
1354 def : Pat<(v4i8 (bitconvert Float32Regs:$s)),
1367 // v4i8 -> f32
