Lines Matching defs:Imm
62 inline SDValue getI32Imm(unsigned Imm) {
63 return CurDAG->getTargetConstant(Imm, MVT::i32);
68 inline SDValue getI64Imm(uint64_t Imm) {
69 return CurDAG->getTargetConstant(Imm, MVT::i64);
73 inline SDValue getSmallIPtrImm(unsigned Imm) {
74 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy());
104 /// a base register plus a signed 16-bit displacement [r+imm].
137 /// be represented by [r+imm], which are preferred.
149 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
275 static bool isIntS16Immediate(SDNode *N, short &Imm) {
279 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
281 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
283 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
286 static bool isIntS16Immediate(SDValue Op, short &Imm) {
287 return isIntS16Immediate(Op.getNode(), Imm);
292 /// operand. If so Imm will receive the 32-bit value.
293 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
295 Imm = cast<ConstantSDNode>(N)->getZExtValue();
302 /// operand. If so Imm will receive the 64-bit value.
303 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
305 Imm = cast<ConstantSDNode>(N)->getZExtValue();
312 // If so Imm will receive the 32 bit value.
313 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
314 return isInt32Immediate(N.getNode(), Imm);
320 // If so Imm will receive the 32 bit value.
321 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
323 && isInt32Immediate(N->getOperand(1).getNode(), Imm);
468 unsigned Imm;
470 if (isInt32Immediate(RHS, Imm)) {
472 if (isUInt<16>(Imm))
474 getI32Imm(Imm & 0xFFFF)), 0);
476 if (isInt<16>((int)Imm))
478 getI32Imm(Imm & 0xFFFF)), 0);
490 getI32Imm(Imm >> 16)), 0);
492 getI32Imm(Imm & 0xFFFF)), 0);
496 if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm))
498 getI32Imm(Imm & 0xFFFF)), 0);
509 uint64_t Imm;
511 if (isInt64Immediate(RHS.getNode(), Imm)) {
513 if (isUInt<16>(Imm))
515 getI32Imm(Imm & 0xFFFF)), 0);
517 if (isInt<16>(Imm))
519 getI32Imm(Imm & 0xFFFF)), 0);
530 if (isUInt<32>(Imm)) {
532 getI64Imm(Imm >> 16)), 0);
534 getI64Imm(Imm & 0xFFFF)), 0);
539 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm))
541 getI64Imm(Imm & 0xFFFF)), 0);
626 unsigned Imm;
631 if (isInt32Immediate(N->getOperand(1), Imm)) {
632 // We can codegen setcc op, imm very efficiently compared to a brcond.
635 if (Imm == 0) {
664 } else if (Imm == ~0U) { // setcc op, -1
762 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
769 if (!isInt<32>(Imm)) {
770 Shift = CountTrailingZeros_64(Imm);
771 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
776 Imm = ImmSh;
779 Remainder = Imm;
781 Imm >>= 32;
789 unsigned Lo = Imm & 0xFFFF;
790 unsigned Hi = (Imm >> 16) & 0xFFFF;
793 if (isInt<16>(Imm)) {
812 if (Imm) {
867 unsigned Imm;
868 if (isInt32Immediate(N->getOperand(1), Imm)) {
870 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
873 N0, getI32Imm(Log2_32(Imm)));
876 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
879 N0, getI32Imm(Log2_32(-Imm)));
977 unsigned Imm, Imm2, SH, MB, ME;
982 if (isInt32Immediate(N->getOperand(1), Imm) &&
983 isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
990 if (isInt32Immediate(N->getOperand(1), Imm) &&
991 isRunOfOnes(Imm, MB, ME) &&
1006 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
1012 if (isInt32Immediate(N->getOperand(1), Imm) &&
1016 Imm = ~(Imm^Imm2);
1017 if (isRunOfOnes(Imm, MB, ME)) {
1036 unsigned Imm, SH, MB, ME;
1037 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
1038 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1048 unsigned Imm, SH, MB, ME;
1049 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
1050 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
