Lines Matching defs:Opcode
85 /// rotate and mask opcode and mask operation.
159 /// Reg in an asm, because the load or store opcode would have to change.
319 // opcode and that it has a immediate integer right operand.
357 unsigned Opcode = N->getOpcode();
362 if (Opcode == ISD::SHL) {
367 } else if (Opcode == ISD::SRL) {
374 } else if (Opcode == ISD::ROTL) {
905 unsigned Opcode;
912 case MVT::f64: Opcode = PPC::LFDU; break;
913 case MVT::f32: Opcode = PPC::LFSU; break;
914 case MVT::i32: Opcode = PPC::LWZU; break;
915 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
917 case MVT::i8: Opcode = PPC::LBZU; break;
924 case MVT::i64: Opcode = PPC::LDU; break;
925 case MVT::i32: Opcode = PPC::LWZU8; break;
926 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
928 case MVT::i8: Opcode = PPC::LBZU8; break;
935 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
939 unsigned Opcode;
946 case MVT::f64: Opcode = PPC::LFDUX; break;
947 case MVT::f32: Opcode = PPC::LFSUX; break;
948 case MVT::i32: Opcode = PPC::LWZUX; break;
949 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break;
951 case MVT::i8: Opcode = PPC::LBZUX; break;
959 case MVT::i64: Opcode = PPC::LDUX; break;
960 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break;
961 case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break;
963 case MVT::i8: Opcode = PPC::LBZUX8; break;
970 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
