Lines Matching refs:IndexReg
192 unsigned IndexReg;
244 return Mem.IndexReg;
470 Res->Mem.IndexReg = 0;
478 unsigned BaseReg, unsigned IndexReg,
483 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
492 Res->Mem.IndexReg = IndexReg;
508 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0);
518 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0;
649 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
653 // Parse [ BaseReg + Scale*IndexReg + Disp ] or [ symbol ]
683 // Handle '[' Scale*IndexReg ']'
686 if (ParseRegister(IndexReg, IdxRegLoc, End))
703 if (ParseRegister(IndexReg, IdxRegLoc, End))
714 if (!IndexReg)
715 ParseRegister(IndexReg, Start, End);
730 if (!BaseReg && !IndexReg)
733 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
829 /// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix
885 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
910 if (ParseRegister(IndexReg, L, L)) return 0;
964 // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
965 if (BaseReg != 0 && IndexReg != 0) {
967 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
968 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)) &&
969 IndexReg != X86::RIZ) {
974 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
975 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) &&
976 IndexReg != X86::EIZ){
982 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
1125 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
1138 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
