Lines Matching refs:IndexReg
479 const MachineOperand &IndexReg = MI.getOperand(Op+2);
486 assert(IndexReg.getReg() == 0 && Is64BitMode &&
507 IndexReg.getReg() == 0 &&
545 assert(IndexReg.getReg() != X86::ESP &&
546 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
579 if (IndexReg.getReg())
580 IndexRegNo = X86_MC::getX86RegNum(IndexReg.getReg());
587 if (IndexReg.getReg())
588 IndexRegNo = X86_MC::getX86RegNum(IndexReg.getReg());
613 const MachineOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
617 (IndexReg.getReg() != 0 &&
618 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
627 const MachineOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
631 (IndexReg.getReg() != 0 &&
632 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
642 const MachineOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
646 (IndexReg.getReg() != 0 &&
647 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg())))
