Lines Matching defs:CC
1778 static bool IsTailCallConvention(CallingConv::ID CC) {
1779 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1796 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1798 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
7764 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7765 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7766 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
8600 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8661 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8677 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8686 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8687 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8697 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8703 bool Invert = (CC == ISD::SETNE) ^
8714 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8734 SDValue CC = Op.getOperand(2);
8750 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8751 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8759 SDValue CC = Op.getOperand(2);
8761 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8940 SDValue CC;
9011 CC = Cond.getOperand(0);
9020 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
9058 CC = DAG.getConstant(X86Cond, MVT::i8);
9072 CC = NewSetCC.getOperand(0);
9080 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9090 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
9105 SDValue Ops[] = { Op2, Op1, CC, Cond };
9141 SDValue CC;
9186 CC = Cond.getOperand(0);
9195 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
9241 CC = DAG.getConstant(X86Cond, MVT::i8);
9253 CC = Cond.getOperand(0).getOperand(0);
9255 Chain, Dest, CC, Cmp);
9256 CC = Cond.getOperand(1).getOperand(0);
9272 CC = DAG.getConstant(CCode, MVT::i8);
9286 Chain, Dest, CC, Cmp);
9290 CC = DAG.getConstant(CCode, MVT::i8);
9303 CC = DAG.getConstant(CCode, MVT::i8);
9329 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9331 Chain, Dest, CC, Cmp);
9332 CC = DAG.getConstant(X86::COND_P, MVT::i8);
9359 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9361 Chain, Dest, CC, Cmp);
9362 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
9381 CC = NewSetCC.getOperand(0);
9389 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9394 Chain, Dest, CC, Cond);
9683 ISD::CondCode CC;
9689 CC = ISD::SETEQ;
9694 CC = ISD::SETLT;
9699 CC = ISD::SETLE;
9704 CC = ISD::SETGT;
9709 CC = ISD::SETGE;
9714 CC = ISD::SETNE;
9719 CC = ISD::SETEQ;
9724 CC = ISD::SETLT;
9729 CC = ISD::SETLE;
9734 CC = ISD::SETGT;
9739 CC = ISD::SETGE;
9744 CC = ISD::SETNE;
9750 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9941 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9942 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
10364 CallingConv::ID CC = Func->getCallingConv();
10367 switch (CC) {
13827 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13830 // Check for x CC y ? x : y.
13833 switch (CC) {
13895 // Check for x CC y ? y : x -- a min/max with reversed arms.
13898 switch (CC) {
14074 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
14075 switch (CC) {
14079 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
14129 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
14136 if (CC != X86::COND_E && CC != X86::COND_NE)
14146 bool needOppositeCond = (CC == X86::COND_E);
14168 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
14170 CC = X86::GetOppositeBranchCondition(CC);
14200 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
14202 CC = X86::GetOppositeBranchCondition(CC);
14213 static SDValue checkFlaggedOrCombine(SDValue Or, X86::CondCode &CC,
14231 if (CC != X86::COND_E && CC != X86::COND_NE)
14300 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
14303 if (CC == X86::COND_E || CC == X86::COND_NE) {
14310 return (CC == X86::COND_E) ? FalseOp : TrueOp;
14316 Flags = checkBoolTestSetCCCombine(Cond, CC);
14319 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
14321 DAG.getConstant(CC, MVT::i8), Flags };
14326 Flags = checkFlaggedOrCombine(Cond, CC, DAG, Subtarget);
14329 DAG.getConstant(CC, MVT::i8), Flags };
14342 CC = X86::GetOppositeBranchCondition(CC);
14351 DAG.getConstant(CC, MVT::i8), Cond);
14368 DAG.getConstant(CC, MVT::i8), Cond);
14406 DAG.getConstant(CC, MVT::i8), Cond);
15817 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
15821 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
15827 addV, DAG.getConstant(0, addV.getValueType()), CC);
15829 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
15835 addV, DAG.getConstant(0, addV.getValueType()), CC);
15845 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
15851 if (CC == X86::COND_B)
15854 DAG.getConstant(CC, MVT::i8), EFLAGS),
15859 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
15861 SDValue Cond = DAG.getConstant(CC, MVT::i8);
15865 Flags = checkFlaggedOrCombine(EFLAGS, CC, DAG, Subtarget);
15867 SDValue Cond = DAG.getConstant(CC, MVT::i8);
15883 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
15887 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
15889 SDValue Cond = DAG.getConstant(CC, MVT::i8);
15894 Flags = checkFlaggedOrCombine(EFLAGS, CC, DAG, Subtarget);
15896 SDValue Cond = DAG.getConstant(CC, MVT::i8);
16007 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
16008 if (CC != X86::COND_E && CC != X86::COND_NE)
16022 if (CC == X86::COND_NE)
16307 AsmPieces[0] == "~{cc}" &&
16325 AsmPieces[0] == "~{cc}" &&
