Lines Matching defs:Result
89 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
92 return Result;
100 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
103 // Inserting UNDEF is Result
105 return Result;
111 EVT ResultVT = Result.getValueType();
122 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
346 // the two-result form to trivial CSE, which is able to combine x/y and x%y
349 // Scalar integer multiply-high is also lowered to use two-result
351 // (low) operations are left as Legal, as there are single-result
352 // instructions for this in x86. Using the two-result multiply instructions
1138 // (result) is 128-bit but the source is 256-bit wide.
1317 /// and store operations as a result of memset, memcpy, and memmove
1513 // Copy the result values into the output registers.
1653 /// LowerCallResult - Lower the result values of a call into the
1670 // Copy all of the result registers out of their specified physreg.
2032 // they may be loaded by deferencing the result of va_next.
2595 // Handle result values, copying them out of physregs into vregs that we
2776 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3731 // The shuffle result is divided into half A and half B. In total the two
3936 bool Result = (Index * ElSize) % 128 == 0;
3938 return Result;
3955 bool Result = (Index * ElSize) % 128 == 0;
3957 return Result;
4569 /// element of the result of the vector shuffle.
5510 SDValue Result;
5512 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5514 Result = DAG.getUNDEF(VT);
5518 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5521 return Result;
5666 // of the result come from the same quadword of one of the two inputs. Undef
5704 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5782 // If we have SSSE3, and all words of the result are from 1 input vector,
5915 // If we have SSSE3, case 1 is generated when all result bytes come from
5919 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5923 // If all result elements are from one input vector, then only translate
5924 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5969 // This word of the result is all undef, skip it.
5973 // This word of the result is already in the correct place, skip it.
6008 // inserting them in the result.
6243 // No input vectors were used! The result is undefined.
6260 // Concatenate the result back
6953 // the result back to FR32 register. It's only worth matching if the
6954 // result has a single use which is a store or a bitcast to i32. And in
6991 // If this is a 256-bit vector result, first extract the 128-bit vector and
7028 // Transform it so it match pextrw which produces a 32-bit result.
7060 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7138 // If this is a 256-bit vector result, first extract the 128-bit vector,
7182 // If this is a 256-bit vector result, first insert into a 128-bit
7206 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7226 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7271 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7275 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7278 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7281 Result);
7284 return Result;
7304 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7307 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7311 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7314 Result);
7316 return Result;
7342 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7345 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7351 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7354 Result);
7360 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7363 return Result;
7374 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7379 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7381 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7385 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7387 Result);
7390 return Result;
7402 SDValue Result;
7406 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7409 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7414 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7416 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7420 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7422 Result);
7428 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7434 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7437 return Result;
7636 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7639 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7838 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7844 Chain = Result.getValue(1);
7845 SDValue InFlag = Result.getValue(2);
7856 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7866 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7871 return Result;
7921 SDValue Result;
7925 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7930 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7935 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7943 // FP constant to bias correct the final result.
8176 // Load the result.
8181 // The node is the result.
8193 // Load the result.
8198 // The node is the result.
8286 // At this point the operands and the result should have the same
8408 // which may be the result of a CAST. We use the variable 'Op', which is the
8416 // leads to the ADD being left around and reselected, with the result being
8451 // If the primary and result isn't used, don't bother using X86ISD::AND,
8586 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
8587 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
8598 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8725 // ones, and then concatenate the result back.
8746 // Issue the operation on the smaller types and concatenate the result back
8879 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8881 // If the logical-not of the result is required, perform that now.
8883 Result = DAG.getNOT(dl, Result, VT);
8885 return Result;
9067 // We know the result of AND is compared against zero. Try to match
9102 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
9376 // We know the result of AND is compared against zero. Try to match
9882 // or testp pattern and a setcc for the result.
10202 SDValue Result = DAG.getNode(X86ISD::RDRAND, dl, VTs, Op.getOperand(0));
10206 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
10209 SDValue(Result.getNode(), 1) };
10214 // Return { result, isValid, chain }.
10215 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
10216 SDValue(Result.getNode(), 2));
10595 // ones, and then concatenate the result back.
10905 // Concatenate the result back
11148 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
11151 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
11157 assert(Subtarget->is64Bit() && "Result not type legalized?");
11375 SDValue Result =
11378 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
11380 Results.push_back(Result.getValue(2));
11383 /// ReplaceNodeResults - Replace a node with an illegal result type
11469 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
11471 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
11473 HalfT, Result.getValue(1));
11941 // result in out1, out2
12680 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
13290 // These nodes' second result is a boolean.
13356 /// inserting the result into the low part of a new 256-bit vector
13372 /// inserting the result into the high part of a new 256-bit vector
13407 // RESULT: V + zero extended
14020 case 1: // result = add base, cond
14021 case 2: // result = lea base( , cond*2)
14022 case 3: // result = lea base(cond, cond*2)
14023 case 4: // result = lea base( , cond*4)
14024 case 5: // result = lea base(cond, cond*4)
14025 case 8: // result = lea base( , cond*8)
14026 case 9: // result = lea base(cond, cond*8)
14130 // Quit if not CMP and SUB with its value result used.
14211 /// updated. If only flag result is used and the result is evaluated from a
14226 // Quit if the value result of OR is used.
14391 case 1: // result = add base, cond
14392 case 2: // result = lea base( , cond*2)
14393 case 3: // result = lea base(cond, cond*2)
14394 case 4: // result = lea base( , cond*4)
14395 case 5: // result = lea base(cond, cond*4)
14396 case 8: // result = lea base( , cond*8)
14397 case 9: // result = lea base(cond, cond*8)
14500 // since the result of setcc_c is all zero's or all ones.
15422 /// then the result of doing a horizontal operation on A and B is
15428 /// operands is UNDEF then the result is UNDEF.
15970 // the result is either zero or one (depending on the input carry bit).
16522 SDValue Result(0, 0);
16533 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
16541 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
16549 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
16557 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
16568 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
16581 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
16593 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
16638 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
16644 if (Result.getNode()) {
16645 Ops.push_back(Result);
