Lines Matching refs:shl
477 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
753 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
989 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
990 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
999 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
1000 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
1007 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1008 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1053 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1054 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1103 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1104 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1126 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1127 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1222 setTargetDAGCombine(ISD::SHL);
4795 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5998 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
7713 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7752 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
8610 if (Op1.getOpcode() == ISD::SHL)
8612 if (Op0.getOpcode() == ISD::SHL) {
9831 Opcode = ISD::SHL;
10697 // Optimize shl/srl/sra with constant shift amount.
10706 if (Op.getOpcode() == ISD::SHL)
10718 if (Op.getOpcode() == ISD::SHL) {
10720 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
10722 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10727 return DAG.getNode(ISD::AND, dl, VT, SHL,
10762 if (Op.getOpcode() == ISD::SHL) {
10764 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
10766 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10771 return DAG.getNode(ISD::AND, dl, VT, SHL,
10807 // Lower SHL with variable shift amount.
10808 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10824 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
11165 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
11321 case ISD::SHL: return LowerShift(Op, DAG);
13993 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
14357 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
14432 /// LEA + SHL, LEA + LEA.
14474 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
14481 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
14499 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
14511 Mask = Mask.shl(ShAmt);
14521 // shl.
14522 // (shl V, 1) -> add V,V
14543 if (N->getOpcode() == ISD::SHL) {
14628 case ISD::SHL:
14940 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
14942 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
16094 case ISD::SHL:
16158 case ISD::SHL:
16204 case ISD::SHL:
16207 // Look out for (store (shl (load), x)).
