| /external/clang/test/CodeGenCXX/ |
| debug-info-byval.cpp | 4 class DAG {
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.h | 27 const ScheduleDAG *DAG;
31 ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_) {}
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| PPCISelLowering.cpp | 1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
418 // We have target-specific dag combine patterns for the following nodes:
734 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.h | 34 /// the DAG and must be handled explicitly by schedulers.
39 SelectionDAG *DAG; // DAG of the current basic block
51 void Run(SelectionDAG *dag, MachineBasicBlock *bb);
82 /// BuildSchedGraph - Build the SUnit graph from the selection dag that we
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| LegalizeTypes.h | 1 //===-- LegalizeTypes.h - Definition of the DAG Type Legalizer class ------===//
37 SelectionDAG &DAG;
68 return TLI.getTypeAction(*DAG.getContext(), VT);
73 return TLI.getTypeAction(*DAG.getContext(), VT) == TargetLowering::TypeLegal;
119 explicit DAGTypeLegalizer(SelectionDAG &dag)
120 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
127 /// top-down traversal of the dag, legalizing types as it goes. Returns
138 SelectionDAG &getDAG() const { return DAG; }
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| LegalizeVectorOps.cpp | 36 SelectionDAG& DAG;
81 VectorLegalizer(SelectionDAG& dag) :
82 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
92 DAG.AssignTopologicalOrder();
93 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
94 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
98 SDValue OldRoot = DAG.getRoot();
100 DAG.setRoot(LegalizedNodes[OldRoot])
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| LegalizeDAG.cpp | 52 SelectionDAG &DAG;
63 explicit SelectionDAGLegalize(SelectionDAG &DAG);
156 DAG.RemoveDeadNode(N);
162 DAG.ReplaceAllUsesWith(Old, New);
166 DAG.ReplaceAllUsesWith(Old, New);
170 DAG.ReplaceAllUsesWith(Old, New);
191 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
205 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
208 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
209 : SelectionDAG::DAGUpdateListener(dag),
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| SelectionDAGBuilder.h | 1 //===-- SelectionDAGBuilder.h - Selection-DAG building --------------------===//
83 /// CurDebugLoc - current file + line number. Changes as we build the DAG.
287 SelectionDAG &DAG;
322 /// no subsequent DAG nodes should be created.
328 SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo,
330 : SDNodeOrder(0), TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
331 DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
354 /// getRoot - Return the current virtual root of the Selection DAG,
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| TargetLowering.cpp | [all...] |
| DAGCombiner.cpp | 1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
40 STATISTIC(NodesCombined , "Number of dag nodes combined");
58 SelectionDAG &DAG;
85 // AA - Used for DAG load/store alias analysis.
162 /// target-specific DAG combines.
165 // Visitation implementation - Implement dag node combining for different
305 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes)
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| SelectionDAGBuilder.cpp | 1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
74 // Limit the width of DAG chains. This is important in general to prevent
75 // prevent DAG-based analysis from blowing up. For example, alias analysis and
78 // future analyses are likely to have the same behavior. Limiting DAG width is
90 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
99 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
104 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
107 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
121 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
124 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2)
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| /external/llvm/include/llvm/CodeGen/ |
| ScoreboardHazardRecognizer.h | 96 const ScheduleDAG *DAG;
109 const ScheduleDAG *DAG,
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| SelectionDAG.h | 1 //===-- llvm/CodeGen/SelectionDAG.h - InstSelection DAG ---------*- C++ -*-===//
123 void checkForCycles(const SelectionDAG *DAG);
126 /// in a low-level Data Dependence DAG representation suitable for instruction
127 /// selection. This DAG is constructed as the first step of instruction
147 /// Root - The root of the entire DAG.
150 /// AllNodes - A linked list of nodes in the current DAG.
182 /// the DAG can optionally implement this interface. This allows the clients
185 /// A DAGUpdateListener automatically registers itself with DAG when it is
189 SelectionDAG &DAG;
192 : Next(D.UpdateListeners), DAG(D)
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonMachineScheduler.h | 51 /// Initialize the strategy after building the DAG for a new region.
52 virtual void initialize(VLIWMachineScheduler *DAG) = 0;
339 VLIWMachineScheduler *DAG;
360 DAG(0), Available(ID, Name+".A"),
390 VLIWMachineScheduler *DAG;
406 DAG(0), TRI(0), Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {}
408 virtual void initialize(VLIWMachineScheduler *dag);
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| HexagonISelLowering.cpp | 1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
11 // into a selection DAG.
265 HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG)
277 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
280 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
281 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
295 DebugLoc dl, SelectionDAG &DAG) const {
301 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
302 getTargetMachine(), RVLocs, *DAG.getContext());
309 if (DAG.getMachineFunction().getRegInfo().liveout_empty())
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| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 621 /// hasTargetDAGCombine - If true, the target has custom DAG combine
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| /external/llvm/lib/CodeGen/ |
| MachineScheduler.cpp | 165 /// consistent with the DAG builder, which traverses the interior of the
168 /// This design avoids exposing scheduling boundaries to the DAG builder,
169 /// simplifying the DAG builder's support for "special" target instructions.
216 // boundary at the bottom of the region. The DAG does not include RegionEnd,
300 /// Initialize the strategy after building the DAG for a new region.
301 virtual void initialize(ScheduleDAGMI *DAG) = 0;
590 // Release all DAG roots for scheduling.
612 /// only includes instructions that have DAG nodes, not scheduling boundaries.
621 // Build the DAG, and compute current register pressure.
638 // Release all DAG roots for scheduling
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| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 1 //===-- MBlazeISelLowering.cpp - MBlaze DAG Lowering Implementation -------===//
11 // selection DAG.
198 SelectionDAG &DAG) const {
201 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
202 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
203 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
204 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
205 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
206 case ISD::VASTART: return LowerVASTART(Op, DAG);
571 SelectionDAG &DAG) const
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| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===//
181 SelectionDAG &DAG) const {
185 case ISD::SRA: return LowerShifts(Op, DAG);
186 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
187 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
188 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
189 case ISD::SETCC: return LowerSETCC(Op, DAG);
190 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
191 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
192 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
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| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 10 // selection DAG.
275 NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
278 Op = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
279 return DAG.getNode(NVPTXISD::Wrapper, dl, getPointerTy(), Op);
444 SelectionDAG &DAG = CLI.DAG;
459 Chain = DAG.getCALLSEQ_START(Chain,
460 DAG.getIntPtrConstant(uniqueCallSite, true));
480 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
482 DAG.getConstant(paramCount, MVT::i32)
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| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
11 // selection DAG.
84 DebugLoc dl, SelectionDAG &DAG) const {
86 MachineFunction &MF = DAG.getMachineFunction();
92 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
93 DAG.getTarget(), RVLocs, *DAG.getContext());
113 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
127 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
128 Chain = DAG.getCopyToReg(Chain, dl, SP::I0, Val, Flag)
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| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 1 //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ---------===//
159 // We have target-specific dag combine patterns for the following nodes:
167 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
170 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
171 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
172 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
173 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
174 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
175 case ISD::LOAD: return LowerLOAD(Op, DAG);
176 case ISD::STORE: return LowerSTORE(Op, DAG);
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| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 1 //===-- SPUISelLowering.cpp - Cell SPU DAG Lowering Implementation --------===//
48 //! Expand a library call into an actual call DAG node
56 ExpandLibCall(RTLIB::Libcall LC, SDValue Op, SelectionDAG &DAG,
61 SDValue InChain = DAG.getEntryNode();
67 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
74 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
79 Op.getNode()->getValueType(0).getTypeForEVT(*DAG.getContext());
86 Callee, Args, DAG, Op.getDebugLoc());
466 // We have target-specific dag combine patterns for the following nodes:
560 LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST)
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| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
11 // selection DAG.
53 static SDValue GetGlobalReg(SelectionDAG &DAG, EVT Ty) {
54 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
55 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
472 static SDValue PerformADDECombine(SDNode *N, SelectionDAG &DAG,
479 SelectMadd(N, &DAG))
485 static SDValue PerformSUBECombine(SDNode *N, SelectionDAG &DAG,
492 SelectMsub(N, &DAG))
498 static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG &DAG,
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| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
11 // selection DAG.
481 // In another words, find a way when "copysign" appears in DAG with vector
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