| /external/llvm/examples/OCaml-Kaleidoscope/Chapter2/ |
| token.ml | 9 | Def | Extern
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| /external/llvm/examples/OCaml-Kaleidoscope/Chapter3/ |
| token.ml | 9 | Def | Extern
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| /external/llvm/examples/OCaml-Kaleidoscope/Chapter4/ |
| token.ml | 9 | Def | Extern
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| /external/llvm/examples/OCaml-Kaleidoscope/Chapter5/ |
| token.ml | 9 | Def | Extern
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| /external/llvm/examples/OCaml-Kaleidoscope/Chapter6/ |
| token.ml | 9 | Def | Extern
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| /external/llvm/examples/OCaml-Kaleidoscope/Chapter7/ |
| token.ml | 9 | Def | Extern
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| /external/llvm/lib/CodeGen/ |
| LiveInterval.cpp | 52 VNInfo *LiveInterval::createDeadDef(SlotIndex Def,
54 assert(!Def.isDead() && "Cannot define a value at the dead slot");
55 iterator I = find(Def);
57 VNInfo *VNI = getNextValue(Def, VNInfoAllocator);
58 ranges.push_back(LiveRange(Def, Def.getDeadSlot(), VNI));
61 if (SlotIndex::isSameInstr(Def, I->start)) {
62 assert(I->start == Def && "Cannot insert def, already live");
63 assert(I->valno->def == Def && "Inconsistent existing value def")
[all...] |
| MachineCopyPropagation.cpp | 110 static bool isNopCopy(MachineInstr *CopyMI, unsigned Def, unsigned Src,
113 if (Def == SrcSrc)
115 if (TRI->isSubRegister(SrcSrc, Def)) {
117 unsigned SubIdx = TRI->getSubRegIndex(SrcSrc, Def);
128 DenseMap<unsigned, MachineInstr*> AvailCopyMap; // Def -> available copies map
129 DenseMap<unsigned, MachineInstr*> CopyMap; // Def -> copies map
130 SourceMap SrcMap; // Src -> Def map
138 unsigned Def = MI->getOperand(0).getReg();
141 if (TargetRegisterInfo::isVirtualRegister(Def) ||
149 if (!ReservedRegs.test(Def) &
[all...] |
| PeepholeOptimizer.cpp | 237 // Both will be live out of the def MBB anyway. Don't extend live range of
300 /// of the def of A with source of B. e.g.
301 /// %vreg0<def> = VMOVSR %vreg1
302 /// %vreg3<def> = VMOVRS %vreg0
312 unsigned Def = 0;
322 Def = Reg;
330 assert(Def && Src && "Malformed bitcast instruction!");
357 if (MRI->getRegClass(SrcSrc) != MRI->getRegClass(Def))
360 MRI->replaceRegWith(Def, SrcSrc);
452 /// and only if the def and use are in the same BB
[all...] |
| ExecutionDepsFix.cpp | 119 int Def;
351 LiveRegs[rx].Def = -(1 << 20);
364 LiveRegs[rx].Def = -1;
381 // Use the most recent predecessor def for each register.
382 LiveRegs[rx].Def = std::max(LiveRegs[rx].Def, fi->second[rx].Def);
422 LiveRegs[i].Def -= CurInstr;
451 // Update def-ages for registers defined by MI.
475 unsigned Clearance = CurInstr - LiveRegs[rx].Def;
[all...] |
| LiveVariables.cpp | 114 assert(MBB != &MF->front() && "Can't find reaching def for virtreg");
133 assert(MRI->getVRegDef(reg) && "Register use before def!");
190 /// FindLastPartialDef - Return the last partial def of the specified register.
199 MachineInstr *Def = PhysRegDef[SubReg];
200 if (!Def)
202 unsigned Dist = DistanceMap[Def];
205 LastDef = Def;
228 /// HandlePhysRegUse - Turn previous partial def's into read/mod/writes. Add
229 /// implicit defs to a machine instruction if there was an earlier def of its
233 // If there was a previous use or a "full" def all is well
[all...] |
| ScheduleDAGInstrs.cpp | 237 assert(MO.isDef() && "expect physreg def");
272 // Adjust the dependence latency using operand def/use
344 // If a def is going to wrap back around to the top of the loop,
423 // The current operand is a def, so we have at least one.
428 // Add output dependence to the next nearest def of this vreg.
434 // is also useful if output latency exceeds def-use latency.
466 MachineInstr *Def = LIS->getInstructionFromIndex(VNI->def);
467 // Phis and other noninstructions (after coalescing) have a NULL Def.
468 if (Def) {
[all...] |
| SplitKit.cpp | 105 if (!SlotIndex::isEarlierInstr(VNI->def, LSP.second) && VNI->def < MBBEnd)
130 UseSlots.push_back((*I)->def);
132 // Get use slots form the use-def chain.
215 // When not live in, the first use should be a def.
217 assert(LVI->start == LVI->valno->def && "Dangling LiveRange start");
218 assert(LVI->start == BI.FirstInstr && "First instr should be a def");
248 // A LiveRange that starts in the middle of the block must be a def.
249 assert(LVI->start == LVI->valno->def && "Dangling LiveRange start");
389 // Keep it as a simple def without any liveness
[all...] |
| BranchFolding.cpp | [all...] |
| LiveIntervalAnalysis.cpp | 182 /// isPartialRedef - Return true if the specified def at the specific index is
193 MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def);
218 assert(!MO.readsReg() && "First def cannot also read virtual register "
288 "PHI def index points at actual instruction.");
299 // e.g. %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
307 // def-and-use register operand.
310 // 80 %reg1041:6<def> = VSHRNv4i16 %reg1034<kill>, 12, pred:14, pred:%reg0
311 // 120 %reg1041:5<def> = VSHRNv4i16 %reg1039<kill>, 12, pred:14, pred:%reg0
324 SlotIndex DefIndex = OldValNo->def.getRegSlot()
[all...] |
| MachineLICM.cpp | 154 unsigned Def;
156 CandidateInfo(MachineInstr *mi, unsigned def, int fi)
157 : MI(mi), Def(def), FI(fi) {}
167 void HoistPostRA(MachineInstr *MI, unsigned Def);
170 /// gather register def and frame object update information.
197 /// HasHighOperandLatency - Compute operand latency between a def of 'Reg'
402 /// gather register def and frame object update information.
410 unsigned Def = 0;
451 // Non-dead implicit def? This cannot be hoisted
[all...] |
| /external/llvm/lib/Analysis/ |
| MemDepPrinter.cpp | 30 Def,
68 return InstTypePair(dep.getInst(), Def);
92 = {"Clobber", "Def", "NonFuncLocal", "Unknown"};
|
| /external/clang/lib/CodeGen/ |
| CGVTables.cpp | 161 const FunctionDecl *Def = 0;
162 if (MD->hasBody(Def) && Def->isOutOfLine())
|
| /external/llvm/include/llvm/Analysis/ |
| MemoryDependenceAnalysis.h | 57 /// Def - This is a dependence on the specified instruction which
65 /// that the def may not be the same type as the query, the pointers
70 /// 3. Dependence queries on calls return Def only when they are
74 Def,
106 assert(Inst && "Def requires inst");
107 return MemDepResult(PairTy(Inst, Def));
132 bool isDef() const { return Value.getInt() == Def; }
|
| /external/llvm/lib/TableGen/ |
| TGLexer.h | 45 Bit, Bits, Class, Code, Dag, Def, Foreach, Defm, Field, In, Int, Let, List,
|
| TGParser.cpp | 225 // Clone the def and add it to the current multiclass
228 // Add all of the values in the superclass into the current def.
268 Record *Def = *j;
270 if (SetValue(Def, SubMultiClass.RefLoc, SMCTArgs[i],
276 Def->resolveReferencesTo(Def->getValue(SMCTArgs[i]));
279 Def->removeValue(SMCTArgs[i]);
349 Error(Loc, "when instantiating this def");
361 Error(Loc, "def already exists: " + IterRec->getNameInitAsString());
376 return K == tgtok::Class || K == tgtok::Def ||
[all...] |
| /external/llvm/utils/TableGen/ |
| SubtargetEmitter.cpp | 94 Record *Def = DefList[i];
97 OS << " const uint64_t " << Def->getName() << " = 1ULL << " << i << ";\n";
106 Record *Def = DefList[i];
109 OS << " " << Def->getName();
|
| DAGISelMatcherGen.cpp | 583 Record *Def = DI->getDef();
584 if (Def->isSubClassOf("Register")) {
586 CGP.getTargetInfo().getRegBank().getReg(Def);
592 if (Def->getName() == "zero_reg") {
600 if (Def->isSubClassOf("RegisterOperand"))
601 Def = Def->getValueAsDef("RegClass");
602 if (Def->isSubClassOf("RegisterClass")) {
603 std::string Value = getQualifiedName(Def) + "RegClassID";
610 if (Def->isSubClassOf("SubRegIndex"))
[all...] |
| /external/llvm/include/llvm/TableGen/ |
| Record.h | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGRRList.cpp | 82 cl::desc("Disable physreg def-use affinity"));
488 /// Call ReleasePred for each predecessor, then update register live def/gen.
538 SUnit *Def = &SUnits[N->getNodeId()];
539 CallSeqEndForStart[Def] = SU;
542 LiveRegDefs[CallResource] = Def;
716 // two-address node as a live range def.
832 // This becomes the nearest def. Note that an earlier def may still be
[all...] |
