| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelDAGToDAG.cpp | 89 inline SDValue getI32Imm(unsigned Imm) {
90 return CurDAG->getTargetConstant(Imm, MVT::i32);
100 static bool isIntS32Immediate(SDNode *N, int32_t &Imm) {
105 Imm = (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
107 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
109 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
112 static bool isIntS32Immediate(SDValue Op, int32_t &Imm) {
113 return isIntS32Immediate(Op.getNode(), Imm);
119 /// can be more efficiently represented with [r+imm].
127 int32_t imm = 0
154 int32_t imm = 0; local
209 SDValue imm = CurDAG->getTargetConstant(0, MVT::i32); local
[all...] |
| /external/llvm/lib/VMCore/ |
| AutoUpgrade.cpp | 236 unsigned Imm;
238 Imm = 0;
240 Imm = 1;
242 Imm = 2;
244 Imm = 3;
246 Imm = 4;
248 Imm = 5;
250 Imm = 6;
252 Imm = 7;
258 CI->getArgOperand(1), Builder.getInt8(Imm));
[all...] |
| /external/llvm/utils/TableGen/ |
| PseudoLoweringEmitter.cpp | 27 enum MapKind { Operand, Imm, Reg };
31 uint64_t Imm; // Integer immedate value.
104 OperandMap[BaseIdx + i].Kind = OpData::Imm;
105 OperandMap[BaseIdx + i].Data.Imm = II->getValue();
235 case OpData::Imm:
237 << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
|
| CodeGenInstruction.h | 299 int64_t Imm;
308 ResultOperand(int64_t I) : Imm(I), Kind(K_Imm) {}
317 int64_t getImm() const { assert(isImm()); return Imm; }
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAddressingModes.h | 106 // reg [asr|lsl|lsr|ror|rrx] imm
109 // reg, the second is the shift amount (or reg0 if not present or imm). The
110 // third operand encodes the shift opcode and the imm if a reg isn't present.
112 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) {
113 return ShOp | (Imm << 3);
122 /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
123 /// the 8-bit imm value.
124 static inline unsigned getSOImmValImm(unsigned Imm) {
125 return Imm & 0xFF
[all...] |
| ARMMCCodeEmitter.cpp | 84 unsigned &Reg, unsigned &Imm,
163 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
432 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
435 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
456 Imm = SImm;
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelDAGToDAG.cpp | 98 inline SDValue getImm(const SDNode *Node, unsigned Imm) {
99 return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
510 int64_t Imm = CN->getSExtValue();
513 AnalyzeImm.Analyze(Imm, Size, false);
|
| /external/llvm/lib/Target/X86/ |
| X86RegisterInfo.cpp | 422 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
424 if (isInt<8>(Imm))
428 if (isInt<8>(Imm))
434 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
436 if (isInt<8>(Imm))
440 if (isInt<8>(Imm))
567 int Imm = (int)(MI.getOperand(i + 3).getImm());
568 int Offset = FIOffset + Imm;
569 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
|
| X86ISelDAGToDAG.cpp | 267 inline SDValue getI8Imm(unsigned Imm) {
268 return CurDAG->getTargetConstant(Imm, MVT::i8);
273 inline SDValue getI32Imm(unsigned Imm) {
274 return CurDAG->getTargetConstant(Imm, MVT::i32);
335 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
336 if (Imm->getAPIntValue().isSignedIntN(8))
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | [all...] |
| Thumb2SizeReduction.cpp | 502 unsigned Imm = MI->getOperand(2).getImm();
506 if (Imm & 3 || Imm > 1020)
521 .addImm(Imm / 4); // The tADDrSPi has an implied scale by four.
631 unsigned Imm = MI->getOperand(2).getImm();
633 if (Imm > Limit)
[all...] |
| ARMAsmPrinter.cpp | 345 int64_t Imm = MO.getImm();
353 O << Imm;
[all...] |
| ARMFastISel.cpp | 121 uint64_t Imm);
130 uint64_t Imm);
133 uint64_t Imm);
368 uint64_t Imm) {
375 .addImm(Imm));
379 .addImm(Imm));
413 uint64_t Imm) {
421 .addImm(Imm));
426 .addImm(Imm));
436 uint64_t Imm) {
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 31 static unsigned translateShiftImm(unsigned imm) {
32 if (imm == 0)
34 return imm;
262 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
501 unsigned Imm = MO.getImm();
502 O << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff);
517 unsigned Imm = MO.getImm();
518 O << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2)
[all...] |
| /external/llvm/lib/Target/MBlaze/AsmParser/ |
| MBlazeAsmParser.cpp | 101 } Imm;
125 Imm = o.Imm;
152 return Imm.Val;
244 Op->Imm.Val = Val;
252 Op->Imm.Val = Val;
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 62 inline SDValue getI32Imm(unsigned Imm) {
63 return CurDAG->getTargetConstant(Imm, MVT::i32);
68 inline SDValue getI64Imm(uint64_t Imm) {
69 return CurDAG->getTargetConstant(Imm, MVT::i64);
73 inline SDValue getSmallIPtrImm(unsigned Imm) {
74 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy());
104 /// a base register plus a signed 16-bit displacement [r+imm].
137 /// be represented by [r+imm], which are preferred.
149 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
275 static bool isIntS16Immediate(SDNode *N, short &Imm) {
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | 389 uint64_t Imm = CI->getZExtValue();
394 isPowerOf2_64(Imm)) {
395 Imm = Log2_64(Imm);
401 isPowerOf2_64(Imm)) {
402 --Imm;
407 Op0IsKill, Imm, VT.getSimpleVT());
[all...] |
| TargetLowering.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 147 } Imm;
205 return Imm.Val;
237 Op->Imm.Val = Val;
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXAsmPrinter.cpp | 491 int Imm = (int)MO.getImm();
493 O << "_" << vecelem[Imm];
495 if((Imm < 0) || (Imm > 3))
499 if((Imm < 4) || (Imm > 7))
503 if(Imm < 0) Imm = 0;
504 O << "_" << vecelem[Imm%4];
507 if((Imm < 0) || (Imm > 1)
[all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 186 } Imm;
227 return Imm.Val;
459 Res->Imm.Val = Val;
[all...] |
| /external/valgrind/main/VEX/priv/ |
| host_amd64_defs.h | 139 UInt imm; member in struct:__anon14562::__anon14563::__anon14564
143 UInt imm; member in struct:__anon14562::__anon14563::__anon14565
176 } Imm;
211 } Imm;
|
| host_ppc_defs.h | 245 } Imm;
273 ULong Imm;
485 Pin_AvShlDbl, /* AV shift-left double by imm */
|
| host_x86_defs.h | 123 UInt imm; member in struct:__anon14847::__anon14848::__anon14849
127 UInt imm; member in struct:__anon14847::__anon14848::__anon14850
160 } Imm;
194 } Imm;
|
