| /external/llvm/lib/Target/Mips/ |
| MipsDirectObjLower.cpp | 58 int Opcode = InstIn.getOpcode();
60 if (Opcode == Mips::DEXT)
77 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU);
83 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
|
| MipsISelDAGToDAG.cpp | 390 unsigned Opcode = Node->getOpcode();
409 switch(Opcode) {
421 if (Opcode == ISD::ADDE) {
447 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
449 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::DMULTu : Mips::DMULT);
474 MultOpc = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
476 MultOpc = (Opcode == ISD::MULHU ? Mips::DMULTu : Mips::DMULT);
|
| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.cpp | 26 unsigned Opcode = MCID.getOpcode();
27 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
|
| MLxExpansionPass.cpp | 144 unsigned Opcode = MCID.getOpcode();
145 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
|
| /external/smali/baksmali/src/main/java/org/jf/baksmali/Adaptors/Format/ |
| OffsetInstructionFormatMethodItem.java | 36 import org.jf.dexlib.Code.Opcode;
72 if (instruction.opcode == Opcode.FILL_ARRAY_DATA) {
75 if (instruction.opcode == Opcode.PACKED_SWITCH) {
78 assert instruction.opcode == Opcode.SPARSE_SWITCH;
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.cpp | 90 PPCHazardRecognizer970::GetInstrType(unsigned Opcode,
94 const MCInstrDesc &MCID = TII.get(Opcode);
145 unsigned Opcode = MI->getOpcode();
148 GetInstrType(Opcode, isFirst, isSingle, isCracked,
182 if (HasCTRSet && (Opcode == PPC::BCTRL_Darwin || Opcode == PPC::BCTRL_SVR4))
203 unsigned Opcode = MI->getOpcode();
206 GetInstrType(Opcode, isFirst, isSingle, isCracked,
211 if (Opcode == PPC::MTCTR || Opcode == PPC::MTCTR8) HasCTRSet = true
[all...] |
| /external/llvm/lib/Target/MBlaze/MCTargetDesc/ |
| MBlazeMCCodeEmitter.cpp | 180 unsigned Opcode = MI.getOpcode();
181 const MCInstrDesc &Desc = MCII.get(Opcode);
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 165 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
166 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
174 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
175 SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
|
| SparcInstrInfo.cpp | 177 unsigned Opcode = I->getOpcode();
178 if (Opcode != SP::BCOND && Opcode != SP::FBCOND)
179 return true; //Unknown Opcode
205 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
|
| /external/webkit/Source/JavaScriptCore/bytecode/ |
| Opcode.h | 196 macro(op_end, 2) // end must be the last opcode in the list
198 #define OPCODE_ID_ENUM(opcode, length) opcode,
208 #define OPCODE_LENGTH(opcode) opcode##_length
210 #define OPCODE_ID_LENGTH_MAP(opcode, length) length,
220 typedef void* Opcode;
222 typedef const void* Opcode;
225 typedef OpcodeID Opcode;
256 static void recordInstruction(int opcode);
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelDAGToDAG.cpp | 190 unsigned Opcode = Node->getOpcode();
201 switch (Opcode) {
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCCodeEmitter.cpp | 120 unsigned Opcode = MI.getOpcode();
121 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && !Binary)
122 llvm_unreachable("unimplemented opcode in EncodeInstruction()");
130 llvm_unreachable("Pseudo opcode found in EncodeInstruction()");
|
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 58 int Opcode = MI->getOpcode();
59 if (Opcode == XCore::LDWFI)
80 int Opcode = MI->getOpcode();
81 if (Opcode == XCore::STWFI)
129 /// the correspondent Branch instruction opcode.
142 /// opcode that matches the cc.
398 /// ReverseBranchCondition - Return the inverse opcode of the
|
| XCoreRegisterInfo.cpp | 138 int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
139 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
143 int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
144 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
245 llvm_unreachable("Unexpected Opcode");
266 llvm_unreachable("Unexpected Opcode");
294 llvm_unreachable("Unexpected Opcode");
309 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
310 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
|
| XCoreFrameLowering.cpp | 54 int Opcode = isU6 ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
55 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg)
69 int Opcode = isU6 ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
70 BuildMI(MBB, I, dl, TII.get(Opcode))
125 int Opcode;
127 Opcode = (isU6) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6;
132 Opcode = (isU6) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
134 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
262 int Opcode = (isU6) ? XCore::RETSP_u6 : XCore::RETSP_lu6;
263 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize)
[all...] |
| /external/llvm/utils/TableGen/ |
| X86RecognizableInstr.h | 38 /// The opcode of the instruction, as used in an MCInst
44 /// The opcode field from the record; this is the opcode used in the Intel
46 uint8_t Opcode;
|
| /external/webkit/Source/WebCore/xml/ |
| XPathPredicate.h | 67 enum Opcode {
70 NumericOp(Opcode, Expression* lhs, Expression* rhs);
75 Opcode m_opcode;
80 enum Opcode { OP_EQ, OP_NE, OP_GT, OP_LT, OP_GE, OP_LE };
81 EqTestOp(Opcode, Expression* lhs, Expression* rhs);
87 Opcode m_opcode;
92 enum Opcode { OP_And, OP_Or };
93 LogicalOp(Opcode, Expression* lhs, Expression* rhs);
99 Opcode m_opcode;
|
| /external/llvm/include/llvm/MC/ |
| MCInst.h | 151 unsigned Opcode;
155 MCInst() : Opcode(0) {}
157 void setOpcode(unsigned Op) { Opcode = Op; }
158 unsigned getOpcode() const { return Opcode; }
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 336 unsigned Opcode = 0;
339 Opcode = MSP430::MOV8rm_POST;
342 Opcode = MSP430::MOV16rm_POST;
348 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(),
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.cpp | 206 unsigned Opcode;
211 case MVT::i8: Opcode = NVPTX::LD_i8_avar; break;
212 case MVT::i16: Opcode = NVPTX::LD_i16_avar; break;
213 case MVT::i32: Opcode = NVPTX::LD_i32_avar; break;
214 case MVT::i64: Opcode = NVPTX::LD_i64_avar; break;
215 case MVT::f32: Opcode = NVPTX::LD_f32_avar; break;
216 case MVT::f64: Opcode = NVPTX::LD_f64_avar; break;
217 case MVT::v2i8: Opcode = NVPTX::LD_v2i8_avar; break;
218 case MVT::v2i16: Opcode = NVPTX::LD_v2i16_avar; break;
219 case MVT::v2i32: Opcode = NVPTX::LD_v2i32_avar; break
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86MCInstLower.cpp | 236 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
252 Inst.setOpcode(Opcode);
258 unsigned Opcode) {
303 Inst.setOpcode(Opcode);
396 unsigned Opcode = OutMI.getOpcode();
399 OutMI.setOpcode(Opcode);
415 unsigned Opcode;
417 default: llvm_unreachable("Invalid opcode");
418 case X86::TAILJMPr: Opcode = X86::JMP32r; break;
420 case X86::TAILJMPd64: Opcode = X86::JMP_1; break
[all...] |
| X86RegisterInfo.cpp | 451 int Opcode = I->getOpcode();
452 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
473 if (Opcode == TII.getCallFrameSetupOpcode()) {
479 assert(Opcode == TII.getCallFrameDestroyOpcode());
502 if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
|
| /external/llvm/lib/Transforms/Utils/ |
| BypassSlowDivision.cpp | 231 unsigned Opcode = J->getOpcode();
232 bool UseDivOp = Opcode == Instruction::SDiv || Opcode == Instruction::UDiv;
233 bool UseRemOp = Opcode == Instruction::SRem || Opcode == Instruction::URem;
234 bool UseSignedOp = Opcode == Instruction::SDiv ||
235 Opcode == Instruction::SRem;
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86Disassembler.cpp | 47 const char *x86DisassemblerGetInstrName(unsigned Opcode, const void *mii) {
49 return MII->getName(Opcode);
351 uint32_t Opcode = mcInst.getOpcode();
358 if (Opcode != X86::BLENDPSrri && Opcode != X86::BLENDPDrri &&
359 Opcode != X86::PBLENDWrri && Opcode != X86::MPSADBWrri &&
360 Opcode != X86::DPPSrri && Opcode != X86::DPPDrri &&
361 Opcode != X86::INSERTPSrr && Opcode != X86::VBLENDPSYrri &
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 440 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
449 // VEX_R: opcode externsion equivalent to REX.R in
471 // VEX_W: opcode specific (use like REX.W, or used for
472 // opcode extension, or ignored, depending on the opcode byte)
481 // 0b00001: implied 0F leading opcode
482 // 0b00010: implied 0F 38 leading opcode bytes
483 // 0b00011: implied 0F 3A leading opcode bytes
500 // VEX_PP: opcode extension providing equivalent
510 // Encode the operand size opcode prefix as needed
[all...] |
