| /external/llvm/lib/Target/ARM/ |
| ARMFrameLowering.h | 26 const ARMSubtarget &STI;
29 explicit ARMFrameLowering(const ARMSubtarget &sti)
30 : TargetFrameLowering(StackGrowsDown, sti.getStackAlignment(), 0, 4),
31 STI(sti) {
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| ARMHazardRecognizer.h | 33 const ARMSubtarget &STI;
42 const ARMSubtarget &sti,
45 TRI(tri), STI(sti), LastMI(0) {}
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| ARMBaseRegisterInfo.h | 78 const ARMSubtarget &STI;
90 const ARMSubtarget &STI);
|
| MLxExpansionPass.cpp | 318 const ARMSubtarget *STI = &Fn.getTarget().getSubtarget<ARMSubtarget>();
319 isA9 = STI->isCortexA9();
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| ARMExpandPseudoInsts.cpp | 44 const ARMSubtarget *STI;
623 if (!STI->hasV6T2Ops() &&
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| Thumb2SizeReduction.cpp | 138 const ARMSubtarget *STI;
220 if (!STI->avoidCPSRPartialUpdate())
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| ARMConstantIslandPass.cpp | 260 const ARMSubtarget *STI;
386 STI = &MF->getTarget().getSubtarget<ARMSubtarget>();
470 if (isThumb2 && !STI->prefers32BitThumb())
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| ARMLoadStoreOptimizer.cpp | 67 const ARMSubtarget *STI;
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.h | 21 const HexagonSubtarget &STI;
25 explicit HexagonFrameLowering(const HexagonSubtarget &sti)
26 : TargetFrameLowering(StackGrowsDown, 8, 0), STI(sti) {
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| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.h | 26 const MSP430Subtarget &STI;
29 explicit MSP430FrameLowering(const MSP430Subtarget &sti)
30 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 2, -2), STI(sti) {
|
| /external/llvm/lib/Target/Mips/ |
| MipsFrameLowering.h | 26 const MipsSubtarget &STI;
29 explicit MipsFrameLowering(const MipsSubtarget &sti)
30 : TargetFrameLowering(StackGrowsDown, sti.hasMips64() ? 16 : 8, 0,
31 sti.hasMips64() ? 16 : 8), STI(sti) {}
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| MipsSEInstrInfo.cpp | 255 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
257 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
258 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
276 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
277 unsigned Size = STI.isABI_N64() ? 64 : 32;
278 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
279 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
280 unsigned ATReg = STI.isABI_N64() ? Mips::AT_64 : Mips::AT;
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeFrameLowering.h | 25 const MBlazeSubtarget &STI;
28 explicit MBlazeFrameLowering(const MBlazeSubtarget &sti)
29 : TargetFrameLowering(TargetFrameLowering::StackGrowsUp, 4, 0), STI(sti) {
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| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.h | 27 const X86Subtarget &STI;
29 explicit X86FrameLowering(const X86TargetMachine &tm, const X86Subtarget &sti)
31 sti.getStackAlignment(),
32 (sti.is64Bit() ? -8 : -4)),
33 TM(tm), STI(sti) {
|
| /external/llvm/include/llvm/MC/ |
| MCDisassembler.h | 58 MCDisassembler(const MCSubtargetInfo &STI) : GetOpInfo(0), SymbolLookUp(0),
60 STI(STI), CommentStream(0) {}
110 const MCSubtargetInfo &STI;
|
| /external/llvm/lib/CodeGen/ |
| LLVMTargetMachine.cpp | 158 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
166 Context->getRegisterInfo(), STI);
172 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
173 MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), MRI, STI,
193 STI, *Context);
266 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
268 STI, *Ctx);
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| /frameworks/compile/mclinker/lib/CodeGen/ |
| LLVMTargetMachine.cpp | 271 const MCSubtargetInfo &STI = getTM().getSubtarget<MCSubtargetInfo>();
276 Context->getRegisterInfo(), STI);
281 MCE = getTarget().get()->createMCCodeEmitter(MII, MRI, STI, *Context);
316 const MCSubtargetInfo &STI = getTM().getSubtarget<MCSubtargetInfo>();
318 getTarget().get()->createMCCodeEmitter(MII, MRI, STI, *Context);
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| /external/llvm/lib/MC/MCDisassembler/ |
| Disassembler.cpp | 72 const MCSubtargetInfo *STI = TheTarget->createMCSubtargetInfo(TripleName, CPU,
74 assert(STI && "Unable to create subtarget info!");
81 MCDisassembler *DisAsm = TheTarget->createMCDisassembler(*STI);
88 *MAI, *MII, *MRI, *STI);
94 STI, MII, Ctx, DisAsm, IP);
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| EDDisassembler.h | 140 llvm::OwningPtr<const llvm::MCSubtargetInfo> STI;
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCCodeEmitter.cpp | 35 const MCSubtargetInfo &STI;
40 MipsMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
42 MCII(mcii), STI(sti) , Ctx(ctx), IsLittleEndian(IsLittle) {}
95 const MCSubtargetInfo &STI,
98 return new MipsMCCodeEmitter(MCII, STI, Ctx, false);
103 const MCSubtargetInfo &STI,
106 return new MipsMCCodeEmitter(MCII, STI, Ctx, true);
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAsmBackend.cpp | 42 const MCSubtargetInfo* STI;
46 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
50 delete STI;
56 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0;
|
| ARMMCCodeEmitter.cpp | 41 const MCSubtargetInfo &STI;
45 ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
47 : MCII(mcii), STI(sti), CTX(ctx) {
54 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
57 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
60 Triple TT(STI.getTargetTriple());
342 const MCSubtargetInfo &STI,
344 return new ARMMCCodeEmitter(MCII, STI, Ctx);
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 34 const MCSubtargetInfo &STI;
37 X86MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
39 : MCII(mcii), STI(sti), Ctx(ctx) {
46 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
51 return (STI.getFeatureBits() & X86::Mode64Bit) == 0;
143 const MCSubtargetInfo &STI,
145 return new X86MCCodeEmitter(MCII, STI, Ctx);
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 38 MCSubtargetInfo &STI;
79 return (STI.getFeatureBits() & Mips::FeatureMips64) != 0;
83 return (STI.getFeatureBits() & Mips::FeatureFP64Bit) != 0;
105 MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
106 : MCTargetAsmParser(), STI(sti), Parser(parser) {
108 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
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| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 34 MCSubtargetInfo &STI;
93 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
96 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(X86::Mode64Bit));
109 X86AsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
110 : MCTargetAsmParser(), STI(sti), Parser(parser) {
113 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
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