| /external/clang/lib/StaticAnalyzer/Core/ |
| SimpleConstraintManager.h | 25 SubEngine &SU;
29 : SU(subengine), BVF(BV) {}
|
| /external/llvm/lib/CodeGen/ |
| DFAPacketizer.cpp | 166 // Generate MI -> SU map.
169 SUnit *SU = &VLIWScheduler->SUnits[i];
170 MIToSUnit[SU->getInstr()] = SU;
|
| CriticalAntiDepBreaker.cpp | 140 /// CriticalPathStep - Return the next SUnit after SU on the bottom-up
142 static const SDep *CriticalPathStep(const SUnit *SU) {
146 for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
430 const SUnit *SU = &SUnits[i];
431 MISUnitMap[SU->getInstr()] = SU;
432 if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency)
433 Max = SU;
[all...] |
| ScheduleDAGInstrs.cpp | 191 /// the exit SU to the register defs and use list. This is because we want to
233 /// MO is an operand of SU's instruction that defines a physical register. Add
234 /// data dependencies from SU to any uses of the physical register.
235 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
236 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
242 unsigned DataLatency = SU->Latency;
250 SUnit *UseSU = UseList[i].SU;
251 if (UseSU == SU)
275 SDep dep(SU, SDep::Data, LDataLatency, *Alias);
278 TII->computeOperandLatency(InstrItins, SU->getInstr(), OperIdx
[all...] |
| MachineScheduler.cpp | 309 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
313 virtual void releaseTopNode(SUnit *SU) = 0;
316 virtual void releaseBottomNode(SUnit *SU) = 0;
426 void releaseSucc(SUnit *SU, SDep *SuccEdge);
427 void releaseSuccessors(SUnit *SU);
428 void releasePred(SUnit *SU, SDep *PredEdge);
429 void releasePredecessors(SUnit *SU);
439 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) {
455 /// releaseSuccessors - Call releaseSucc on each of SU's successors.
456 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) {
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ResourcePriorityQueue.cpp | 71 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) {
73 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
108 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU,
111 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
146 static unsigned numberCtrlDepsInSU(SUnit *SU) {
148 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
156 static unsigned numberCtrlPredInSU(SUnit *SU) {
652 SUnit *su = q.pop(); local
[all...] |
| ScheduleDAGSDNodes.cpp | 78 SUnit *SU = &SUnits.back();
83 SU->SchedulingPref = Sched::None;
85 SU->SchedulingPref = TLI.getSchedulingPreference(N);
86 return SU;
90 SUnit *SU = newSUnit(Old->getNode());
91 SU->OrigNode = Old->OrigNode;
92 SU->Latency = Old->Latency;
93 SU->isVRegCycle = Old->isVRegCycle;
94 SU->isCall = Old->isCall;
95 SU->isCallOp = Old->isCallOp
[all...] |
| ScheduleDAGRRList.cpp | 177 /// IsReachable - Checks if SU is reachable from TargetSU.
178 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) {
179 return Topo.IsReachable(SU, TargetSU);
182 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will
184 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) {
185 return Topo.WillCreateCycle(SU, TargetSU);
188 /// AddPred - adds a predecessor edge to SUnit SU.
191 void AddPred(SUnit *SU, const SDep &D) {
192 Topo.AddPred(SU, D.getSUnit());
193 SU->addPred(D)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ScheduleDAGInstrs.h | 102 SUnit *SU;
104 VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {}
114 SUnit *SU;
117 PhysRegSUOper(SUnit *su, int op): SU(su), OpIdx(op) {}
298 virtual void computeLatency(SUnit *SU);
311 virtual void dumpNode(const SUnit *SU) const
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonMachineScheduler.cpp | 64 void VLIWMachineScheduler::releaseSucc(SUnit *SU, SDep *SuccEdge) {
80 /// releaseSuccessors - Call releaseSucc on each of SU's successors.
81 void VLIWMachineScheduler::releaseSuccessors(SUnit *SU) {
82 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
84 releaseSucc(SU, &*I);
92 void VLIWMachineScheduler::releasePred(SUnit *SU, SDep *PredEdge) {
108 /// releasePredecessors - Call releasePred on each of SU's predecessors.
109 void VLIWMachineScheduler::releasePredecessors(SUnit *SU) {
110 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end()
[all...] |
| HexagonMachineScheduler.h | 61 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
65 virtual void releaseTopNode(SUnit *SU) = 0;
68 virtual void releaseBottomNode(SUnit *SU) = 0;
91 // SU is in this queue if it's NodeQueueID is a superset of this ID.
92 bool isInQueue(SUnit *SU) const { return (SU->NodeQueueId & ID); }
104 iterator find(SUnit *SU) {
105 return std::find(Queue.begin(), Queue.end(), SU);
108 void push(SUnit *SU) {
109 Queue.push_back(SU);
[all...] |
| HexagonVLIWPacketizer.cpp | [all...] |
| /frameworks/opt/calendar/src/com/android/calendarcommon2/ |
| EventRecurrence.java | 41 public static final int SU = 0x00010000;
55 public int wkst; // SU, MO, TU, etc.
129 sParseWeekdayMap.put("SU", SU);
164 * Converts one of the Calendar.SUNDAY constants to the SU, MO, etc.
173 return SU;
196 return SU;
217 case SU:
237 * Converts one of the SU, MO, etc. constants to the Calendar.SUNDAY
245 case SU
[all...] |
