| /external/llvm/lib/Target/Mips/ |
| MipsSERegisterInfo.h | 24 const MipsSEInstrInfo &TII;
28 const MipsSEInstrInfo &TII);
|
| Mips16FrameLowering.cpp | 32 const MipsInstrInfo &TII =
43 BuildMI(MBB, MBBI, dl, TII.get(Mips::SaveRaF16)).addImm(StackSize);
50 const MipsInstrInfo &TII =
61 BuildMI(MBB, MBBI, dl, TII.get(Mips::RestoreRaF16)).addImm(StackSize);
|
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.h | 28 const TargetInstrInfo &TII;
43 XCoreRegisterInfo(const TargetInstrInfo &tii);
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430RegisterInfo.h | 30 const TargetInstrInfo &TII;
36 MSP430RegisterInfo(MSP430TargetMachine &tm, const TargetInstrInfo &tii);
|
| MSP430BranchSelector.cpp | 55 const MSP430InstrInfo *TII =
70 BlockSize += TII->GetInstSizeInBytes(MBBI);
107 MBBStartOffset += TII->GetInstSizeInBytes(I);
154 TII->ReverseBranchCondition(Cond);
155 BuildMI(MBB, I, dl, TII->get(MSP430::JCC))
161 I = BuildMI(MBB, I, dl, TII->get(MSP430::Bi)).addMBB(Dest);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.h | 32 const TargetInstrInfo &TII;
34 PPCRegisterInfo(const PPCSubtarget &SubTarget, const TargetInstrInfo &tii);
|
| PPCHazardRecognizers.h | 46 const TargetInstrInfo &TII;
67 PPCHazardRecognizer970(const TargetInstrInfo &TII);
|
| PPCBranchSelector.cpp | 56 const PPCInstrInfo *TII =
71 BlockSize += TII->GetInstSizeInBytes(MBBI);
107 MBBStartOffset += TII->GetInstSizeInBytes(I);
152 BuildMI(MBB, I, dl, TII->get(PPC::BCC))
155 BuildMI(MBB, I, dl, TII->get(PPC::BDZ)).addImm(2);
157 BuildMI(MBB, I, dl, TII->get(PPC::BDZ8)).addImm(2);
159 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ)).addImm(2);
161 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ8)).addImm(2);
167 I = BuildMI(MBB, I, dl, TII->get(PPC::B)).addMBB(Dest);
|
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.h | 30 const TargetInstrInfo &TII;
32 SparcRegisterInfo(SparcSubtarget &st, const TargetInstrInfo &tii);
|
| SparcFrameLowering.cpp | 32 const SparcInstrInfo &TII =
55 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVEri), SP::O6)
61 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
63 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
65 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVErr), SP::O6)
73 const SparcInstrInfo &TII =
78 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineSSAUpdater.h | 52 const TargetInstrInfo *TII;
|
| DFAPacketizer.h | 96 const TargetInstrInfo *TII;
|
| FastISel.h | 58 const TargetInstrInfo &TII;
|
| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.h | 31 const ARMBaseInstrInfo &TII;
40 const ARMBaseInstrInfo &tii,
44 ScoreboardHazardRecognizer(ItinData, DAG, "post-RA-sched"), TII(tii),
|
| ARMBaseRegisterInfo.h | 77 const ARMBaseInstrInfo &TII;
89 explicit ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
|
| /external/llvm/lib/Target/CellSPU/ |
| SPURegisterInfo.h | 31 const TargetInstrInfo &TII;
37 SPURegisterInfo(const SPUSubtarget &subtarget, const TargetInstrInfo &tii);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonRegisterInfo.h | 47 const HexagonInstrInfo &TII;
49 HexagonRegisterInfo(HexagonSubtarget &st, const HexagonInstrInfo &tii);
|
| HexagonExpandPredSpillCode.cpp | 66 const HexagonInstrInfo *TII = QTM.getInstrInfo();
87 if (!TII->isValidOffset(Hexagon::STriw_indexed, Offset)) {
88 if (!TII->isValidOffset(Hexagon::ADD_ri, Offset)) {
90 TII->get(Hexagon::CONST32_Int_Real),
92 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_rr),
95 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
98 TII->get(Hexagon::STriw_indexed))
102 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri),
104 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
107 TII->get(Hexagon::STriw_indexed)
[all...] |
| HexagonSplitTFRCondSets.cpp | 74 const TargetInstrInfo *TII = QTM.getInstrInfo();
106 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc1),
110 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc2),
126 TII->get(Hexagon::TFR_cPt), DestReg).
131 TII->get(Hexagon::TFRI_cNotPt), DestReg).
136 TII->get(Hexagon::TFRI_cNotPt_f), DestReg).
152 TII->get(Hexagon::TFRI_cPt), DestReg).
157 TII->get(Hexagon::TFRI_cPt_f), DestReg).
166 TII->get(Hexagon::TFR_cNotPt), DestReg).
182 TII->get(Hexagon::TFRI_cPt)
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeRegisterInfo.h | 40 const TargetInstrInfo &TII;
43 const TargetInstrInfo &tii);
|
| /external/llvm/lib/CodeGen/ |
| CriticalAntiDepBreaker.h | 37 const TargetInstrInfo *TII;
|
| DeadMachineInstructionElim.cpp | 34 const TargetInstrInfo *TII;
63 if (!MI->isSafeToMove(TII, 0, SawStore) && !MI->isPHI())
91 TII = MF.getTarget().getInstrInfo();
|
| ProcessImplicitDefs.cpp | 28 const TargetInstrInfo *TII;
92 UserMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
144 TII = MF.getTarget().getInstrInfo();
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.h | 32 const TargetInstrInfo *TII;
|
| /external/llvm/lib/Target/X86/ |
| X86RegisterInfo.h | 30 const TargetInstrInfo &TII;
59 X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii);
|
