/external/llvm/lib/Target/ARM/ |
Thumb2RegisterInfo.h | 36 ARMCC::CondCodes Pred = ARMCC::AL,
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Thumb2RegisterInfo.cpp | 40 ARMCC::CondCodes Pred, unsigned PredReg, 50 .addConstantPoolIndex(Idx).addImm((int64_t)ARMCC::AL).addReg(0)
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Thumb2ITBlockPass.cpp | 43 ARMCC::CondCodes CC, ARMCC::CondCodes OCC, 105 ARMCC::CondCodes CC, ARMCC::CondCodes OCC, 153 ARMCC::CondCodes NCC = getITInstrPredicate(I, NPredReg); 170 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg); 171 if (CC == ARMCC::AL) { 193 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC); 206 ARMCC::CondCodes NCC = getITInstrPredicate(NMI, NPredReg) [all...] |
Thumb1RegisterInfo.h | 42 ARMCC::CondCodes Pred = ARMCC::AL,
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Thumb2InstrInfo.h | 70 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
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ARMInstrInfo.cpp | 36 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 42 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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ARMBaseInstrInfo.h | 77 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const { 79 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm() 80 : ARMCC::AL; 315 return MIB.addImm((int64_t)ARMCC::AL).addReg(0); 358 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg); 379 ARMCC::CondCodes Pred, unsigned PredReg, 385 ARMCC::CondCodes Pred, unsigned PredReg,
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ARMBaseInstrInfo.cpp | 157 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 414 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0); 427 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0); 435 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 436 Cond[0].setImm(ARMCC::getOppositeCondition(CC)); 446 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL) 453 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL; 483 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm() [all...] |
ARMAsmPrinter.cpp | [all...] |
Thumb2InstrInfo.cpp | 39 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 61 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg); 63 if (CC != ARMCC::AL) 71 if (CC != ARMCC::AL) { 109 return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL; 180 ARMCC::CondCodes Pred, unsigned PredReg, 404 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) { 566 ARMCC::CondCodes 570 return ARMCC::AL;
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ARMBaseRegisterInfo.h | 168 ARMCC::CondCodes Pred = ARMCC::AL,
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Thumb1InstrInfo.cpp | 33 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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Thumb2SizeReduction.cpp | 154 bool is2Addr, ARMCC::CondCodes Pred, 254 bool is2Addr, ARMCC::CondCodes Pred, 258 if (Pred == ARMCC::AL) { 510 if (MI->getOperand(3).getImm() != ARMCC::AL) 545 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) { 644 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); 646 if (Pred != ARMCC::AL) { 736 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); 738 if (Pred != ARMCC::AL) { [all...] |
ARMLoadStoreOptimizer.cpp | 95 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, 108 ARMCC::CondCodes Pred, 115 ARMCC::CondCodes Pred, unsigned PredReg, 285 int Opcode, ARMCC::CondCodes Pred, 371 ARMCC::CondCodes Pred, unsigned PredReg, 448 ARMCC::CondCodes Pred, unsigned PredReg, 531 ARMCC::CondCodes Pred, unsigned PredReg) { 564 ARMCC::CondCodes Pred, unsigned PredReg) { 719 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); 872 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg) [all...] |
ARMConstantIslandPass.cpp | [all...] |
ARMBaseRegisterInfo.cpp | 709 ARMCC::CondCodes Pred, 749 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { 785 ARMCC::CondCodes Pred = (PIdx == -1) 786 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm(); [all...] |
ARMFastISel.cpp | [all...] |
MLxExpansionPass.cpp | 218 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NextOp).getImm();
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ARMISelLowering.cpp | [all...] |
ARMFrameLowering.cpp | 126 ARMCC::AL, 0, TII, MIFlags); 129 ARMCC::AL, 0, TII, MIFlags); 330 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 393 ARMCC::AL, 0, TII); 405 ARMCC::AL, 0, TII); 414 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 456 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0); [all...] |
Thumb1RegisterInfo.cpp | 70 ARMCC::CondCodes Pred, unsigned PredReg, 126 ARMCC::AL, 0, MIFlags); 414 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
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/external/llvm/lib/Target/ARM/MCTargetDesc/ |
ARMBaseInfo.h | 26 namespace ARMCC { 66 } // namespace ARMCC 68 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) { 70 case ARMCC::EQ: return "eq"; 71 case ARMCC::NE: return "ne"; 72 case ARMCC::HS: return "hs"; 73 case ARMCC::LO: return "lo"; 74 case ARMCC::MI: return "mi"; 75 case ARMCC::PL: return "pl"; 76 case ARMCC::VS: return "vs" [all...] |
ARMMCTargetDesc.cpp | 203 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL) 210 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
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/external/llvm/lib/Target/ARM/AsmParser/ |
ARMAsmParser.cpp | 53 ARMCC::CondCodes Cond; // Condition for IT block. 313 ARMCC::CondCodes Val; 493 ARMCC::CondCodes getCondCode() const { [all...] |
/external/llvm/lib/Target/ARM/InstPrinter/ |
ARMInstPrinter.cpp | 746 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); 750 else if (CC != ARMCC::AL) 757 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); [all...] |