1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/ARMBaseInfo.h" 11 #include "MCTargetDesc/ARMAddressingModes.h" 12 #include "MCTargetDesc/ARMMCExpr.h" 13 #include "llvm/MC/MCParser/MCAsmLexer.h" 14 #include "llvm/MC/MCParser/MCAsmParser.h" 15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 16 #include "llvm/MC/MCAsmInfo.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCStreamer.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCInstrDesc.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCSubtargetInfo.h" 24 #include "llvm/MC/MCTargetAsmParser.h" 25 #include "llvm/Support/MathExtras.h" 26 #include "llvm/Support/SourceMgr.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include "llvm/Support/raw_ostream.h" 29 #include "llvm/ADT/BitVector.h" 30 #include "llvm/ADT/OwningPtr.h" 31 #include "llvm/ADT/STLExtras.h" 32 #include "llvm/ADT/SmallVector.h" 33 #include "llvm/ADT/StringSwitch.h" 34 #include "llvm/ADT/Twine.h" 35 36 using namespace llvm; 37 38 namespace { 39 40 class ARMOperand; 41 42 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane }; 43 44 class ARMAsmParser : public MCTargetAsmParser { 45 MCSubtargetInfo &STI; 46 MCAsmParser &Parser; 47 const MCRegisterInfo *MRI; 48 49 // Map of register aliases registers via the .req directive. 50 StringMap<unsigned> RegisterReqs; 51 52 struct { 53 ARMCC::CondCodes Cond; // Condition for IT block. 54 unsigned Mask:4; // Condition mask for instructions. 55 // Starting at first 1 (from lsb). 56 // '1' condition as indicated in IT. 57 // '0' inverse of condition (else). 58 // Count of instructions in IT block is 59 // 4 - trailingzeroes(mask) 60 61 bool FirstCond; // Explicit flag for when we're parsing the 62 // First instruction in the IT block. It's 63 // implied in the mask, so needs special 64 // handling. 65 66 unsigned CurPosition; // Current position in parsing of IT 67 // block. In range [0,3]. Initialized 68 // according to count of instructions in block. 69 // ~0U if no active IT block. 70 } ITState; 71 bool inITBlock() { return ITState.CurPosition != ~0U;} 72 void forwardITPosition() { 73 if (!inITBlock()) return; 74 // Move to the next instruction in the IT block, if there is one. If not, 75 // mark the block as done. 76 unsigned TZ = CountTrailingZeros_32(ITState.Mask); 77 if (++ITState.CurPosition == 5 - TZ) 78 ITState.CurPosition = ~0U; // Done with the IT block after this. 79 } 80 81 82 MCAsmParser &getParser() const { return Parser; } 83 MCAsmLexer &getLexer() const { return Parser.getLexer(); } 84 85 bool Warning(SMLoc L, const Twine &Msg, 86 ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) { 87 return Parser.Warning(L, Msg, Ranges); 88 } 89 bool Error(SMLoc L, const Twine &Msg, 90 ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) { 91 return Parser.Error(L, Msg, Ranges); 92 } 93 94 int tryParseRegister(); 95 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &); 96 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &); 97 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &); 98 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &); 99 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic); 100 bool parsePrefix(ARMMCExpr::VariantKind &RefKind); 101 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, 102 unsigned &ShiftAmount); 103 bool parseDirectiveWord(unsigned Size, SMLoc L); 104 bool parseDirectiveThumb(SMLoc L); 105 bool parseDirectiveARM(SMLoc L); 106 bool parseDirectiveThumbFunc(SMLoc L); 107 bool parseDirectiveCode(SMLoc L); 108 bool parseDirectiveSyntax(SMLoc L); 109 bool parseDirectiveReq(StringRef Name, SMLoc L); 110 bool parseDirectiveUnreq(SMLoc L); 111 bool parseDirectiveArch(SMLoc L); 112 bool parseDirectiveEabiAttr(SMLoc L); 113 114 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, 115 bool &CarrySetting, unsigned &ProcessorIMod, 116 StringRef &ITMask); 117 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 118 bool &CanAcceptPredicationCode); 119 120 bool isThumb() const { 121 // FIXME: Can tablegen auto-generate this? 122 return (STI.getFeatureBits() & ARM::ModeThumb) != 0; 123 } 124 bool isThumbOne() const { 125 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0; 126 } 127 bool isThumbTwo() const { 128 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2); 129 } 130 bool hasV6Ops() const { 131 return STI.getFeatureBits() & ARM::HasV6Ops; 132 } 133 bool hasV7Ops() const { 134 return STI.getFeatureBits() & ARM::HasV7Ops; 135 } 136 void SwitchMode() { 137 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); 138 setAvailableFeatures(FB); 139 } 140 bool isMClass() const { 141 return STI.getFeatureBits() & ARM::FeatureMClass; 142 } 143 144 /// @name Auto-generated Match Functions 145 /// { 146 147 #define GET_ASSEMBLER_HEADER 148 #include "ARMGenAsmMatcher.inc" 149 150 /// } 151 152 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&); 153 OperandMatchResultTy parseCoprocNumOperand( 154 SmallVectorImpl<MCParsedAsmOperand*>&); 155 OperandMatchResultTy parseCoprocRegOperand( 156 SmallVectorImpl<MCParsedAsmOperand*>&); 157 OperandMatchResultTy parseCoprocOptionOperand( 158 SmallVectorImpl<MCParsedAsmOperand*>&); 159 OperandMatchResultTy parseMemBarrierOptOperand( 160 SmallVectorImpl<MCParsedAsmOperand*>&); 161 OperandMatchResultTy parseProcIFlagsOperand( 162 SmallVectorImpl<MCParsedAsmOperand*>&); 163 OperandMatchResultTy parseMSRMaskOperand( 164 SmallVectorImpl<MCParsedAsmOperand*>&); 165 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O, 166 StringRef Op, int Low, int High); 167 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 168 return parsePKHImm(O, "lsl", 0, 31); 169 } 170 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 171 return parsePKHImm(O, "asr", 1, 32); 172 } 173 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&); 174 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&); 175 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&); 176 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&); 177 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&); 178 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&); 179 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&); 180 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&); 181 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index); 182 183 // Asm Match Converter Methods 184 void cvtT2LdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &); 185 void cvtT2StrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &); 186 void cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, 187 const SmallVectorImpl<MCParsedAsmOperand*> &); 188 void cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, 189 const SmallVectorImpl<MCParsedAsmOperand*> &); 190 void cvtLdWriteBackRegAddrMode2(MCInst &Inst, 191 const SmallVectorImpl<MCParsedAsmOperand*> &); 192 void cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, 193 const SmallVectorImpl<MCParsedAsmOperand*> &); 194 void cvtStWriteBackRegAddrModeImm12(MCInst &Inst, 195 const SmallVectorImpl<MCParsedAsmOperand*> &); 196 void cvtStWriteBackRegAddrMode2(MCInst &Inst, 197 const SmallVectorImpl<MCParsedAsmOperand*> &); 198 void cvtStWriteBackRegAddrMode3(MCInst &Inst, 199 const SmallVectorImpl<MCParsedAsmOperand*> &); 200 void cvtLdExtTWriteBackImm(MCInst &Inst, 201 const SmallVectorImpl<MCParsedAsmOperand*> &); 202 void cvtLdExtTWriteBackReg(MCInst &Inst, 203 const SmallVectorImpl<MCParsedAsmOperand*> &); 204 void cvtStExtTWriteBackImm(MCInst &Inst, 205 const SmallVectorImpl<MCParsedAsmOperand*> &); 206 void cvtStExtTWriteBackReg(MCInst &Inst, 207 const SmallVectorImpl<MCParsedAsmOperand*> &); 208 void cvtLdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &); 209 void cvtStrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &); 210 void cvtLdWriteBackRegAddrMode3(MCInst &Inst, 211 const SmallVectorImpl<MCParsedAsmOperand*> &); 212 void cvtThumbMultiply(MCInst &Inst, 213 const SmallVectorImpl<MCParsedAsmOperand*> &); 214 void cvtVLDwbFixed(MCInst &Inst, 215 const SmallVectorImpl<MCParsedAsmOperand*> &); 216 void cvtVLDwbRegister(MCInst &Inst, 217 const SmallVectorImpl<MCParsedAsmOperand*> &); 218 void cvtVSTwbFixed(MCInst &Inst, 219 const SmallVectorImpl<MCParsedAsmOperand*> &); 220 void cvtVSTwbRegister(MCInst &Inst, 221 const SmallVectorImpl<MCParsedAsmOperand*> &); 222 bool validateInstruction(MCInst &Inst, 223 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 224 bool processInstruction(MCInst &Inst, 225 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 226 bool shouldOmitCCOutOperand(StringRef Mnemonic, 227 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 228 229 public: 230 enum ARMMatchResultTy { 231 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY, 232 Match_RequiresNotITBlock, 233 Match_RequiresV6, 234 Match_RequiresThumb2, 235 #define GET_OPERAND_DIAGNOSTIC_TYPES 236 #include "ARMGenAsmMatcher.inc" 237 238 }; 239 240 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser) 241 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) { 242 MCAsmParserExtension::Initialize(_Parser); 243 244 // Cache the MCRegisterInfo. 245 MRI = &getContext().getRegisterInfo(); 246 247 // Initialize the set of available features. 248 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 249 250 // Not in an ITBlock to start with. 251 ITState.CurPosition = ~0U; 252 } 253 254 // Implementation of the MCTargetAsmParser interface: 255 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); 256 bool ParseInstruction(StringRef Name, SMLoc NameLoc, 257 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 258 bool ParseDirective(AsmToken DirectiveID); 259 260 unsigned checkTargetMatchPredicate(MCInst &Inst); 261 262 bool MatchAndEmitInstruction(SMLoc IDLoc, 263 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 264 MCStreamer &Out); 265 266 unsigned getMCInstOperandNum(unsigned Kind, MCInst &Inst, 267 const SmallVectorImpl<MCParsedAsmOperand*> &Operands, 268 unsigned OperandNum, unsigned &NumMCOperands) { 269 return getMCInstOperandNumImpl(Kind, Inst, Operands, OperandNum, NumMCOperands); 270 } 271 }; 272 } // end anonymous namespace 273 274 namespace { 275 276 /// ARMOperand - Instances of this class represent a parsed ARM machine 277 /// instruction. 278 class ARMOperand : public MCParsedAsmOperand { 279 enum KindTy { 280 k_CondCode, 281 k_CCOut, 282 k_ITCondMask, 283 k_CoprocNum, 284 k_CoprocReg, 285 k_CoprocOption, 286 k_Immediate, 287 k_MemBarrierOpt, 288 k_Memory, 289 k_PostIndexRegister, 290 k_MSRMask, 291 k_ProcIFlags, 292 k_VectorIndex, 293 k_Register, 294 k_RegisterList, 295 k_DPRRegisterList, 296 k_SPRRegisterList, 297 k_VectorList, 298 k_VectorListAllLanes, 299 k_VectorListIndexed, 300 k_ShiftedRegister, 301 k_ShiftedImmediate, 302 k_ShifterImmediate, 303 k_RotateImmediate, 304 k_BitfieldDescriptor, 305 k_Token 306 } Kind; 307 308 SMLoc StartLoc, EndLoc; 309 SmallVector<unsigned, 8> Registers; 310 311 union { 312 struct { 313 ARMCC::CondCodes Val; 314 } CC; 315 316 struct { 317 unsigned Val; 318 } Cop; 319 320 struct { 321 unsigned Val; 322 } CoprocOption; 323 324 struct { 325 unsigned Mask:4; 326 } ITMask; 327 328 struct { 329 ARM_MB::MemBOpt Val; 330 } MBOpt; 331 332 struct { 333 ARM_PROC::IFlags Val; 334 } IFlags; 335 336 struct { 337 unsigned Val; 338 } MMask; 339 340 struct { 341 const char *Data; 342 unsigned Length; 343 } Tok; 344 345 struct { 346 unsigned RegNum; 347 } Reg; 348 349 // A vector register list is a sequential list of 1 to 4 registers. 350 struct { 351 unsigned RegNum; 352 unsigned Count; 353 unsigned LaneIndex; 354 bool isDoubleSpaced; 355 } VectorList; 356 357 struct { 358 unsigned Val; 359 } VectorIndex; 360 361 struct { 362 const MCExpr *Val; 363 } Imm; 364 365 /// Combined record for all forms of ARM address expressions. 366 struct { 367 unsigned BaseRegNum; 368 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset 369 // was specified. 370 const MCConstantExpr *OffsetImm; // Offset immediate value 371 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL 372 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg 373 unsigned ShiftImm; // shift for OffsetReg. 374 unsigned Alignment; // 0 = no alignment specified 375 // n = alignment in bytes (2, 4, 8, 16, or 32) 376 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit) 377 } Memory; 378 379 struct { 380 unsigned RegNum; 381 bool isAdd; 382 ARM_AM::ShiftOpc ShiftTy; 383 unsigned ShiftImm; 384 } PostIdxReg; 385 386 struct { 387 bool isASR; 388 unsigned Imm; 389 } ShifterImm; 390 struct { 391 ARM_AM::ShiftOpc ShiftTy; 392 unsigned SrcReg; 393 unsigned ShiftReg; 394 unsigned ShiftImm; 395 } RegShiftedReg; 396 struct { 397 ARM_AM::ShiftOpc ShiftTy; 398 unsigned SrcReg; 399 unsigned ShiftImm; 400 } RegShiftedImm; 401 struct { 402 unsigned Imm; 403 } RotImm; 404 struct { 405 unsigned LSB; 406 unsigned Width; 407 } Bitfield; 408 }; 409 410 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 411 public: 412 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() { 413 Kind = o.Kind; 414 StartLoc = o.StartLoc; 415 EndLoc = o.EndLoc; 416 switch (Kind) { 417 case k_CondCode: 418 CC = o.CC; 419 break; 420 case k_ITCondMask: 421 ITMask = o.ITMask; 422 break; 423 case k_Token: 424 Tok = o.Tok; 425 break; 426 case k_CCOut: 427 case k_Register: 428 Reg = o.Reg; 429 break; 430 case k_RegisterList: 431 case k_DPRRegisterList: 432 case k_SPRRegisterList: 433 Registers = o.Registers; 434 break; 435 case k_VectorList: 436 case k_VectorListAllLanes: 437 case k_VectorListIndexed: 438 VectorList = o.VectorList; 439 break; 440 case k_CoprocNum: 441 case k_CoprocReg: 442 Cop = o.Cop; 443 break; 444 case k_CoprocOption: 445 CoprocOption = o.CoprocOption; 446 break; 447 case k_Immediate: 448 Imm = o.Imm; 449 break; 450 case k_MemBarrierOpt: 451 MBOpt = o.MBOpt; 452 break; 453 case k_Memory: 454 Memory = o.Memory; 455 break; 456 case k_PostIndexRegister: 457 PostIdxReg = o.PostIdxReg; 458 break; 459 case k_MSRMask: 460 MMask = o.MMask; 461 break; 462 case k_ProcIFlags: 463 IFlags = o.IFlags; 464 break; 465 case k_ShifterImmediate: 466 ShifterImm = o.ShifterImm; 467 break; 468 case k_ShiftedRegister: 469 RegShiftedReg = o.RegShiftedReg; 470 break; 471 case k_ShiftedImmediate: 472 RegShiftedImm = o.RegShiftedImm; 473 break; 474 case k_RotateImmediate: 475 RotImm = o.RotImm; 476 break; 477 case k_BitfieldDescriptor: 478 Bitfield = o.Bitfield; 479 break; 480 case k_VectorIndex: 481 VectorIndex = o.VectorIndex; 482 break; 483 } 484 } 485 486 /// getStartLoc - Get the location of the first token of this operand. 487 SMLoc getStartLoc() const { return StartLoc; } 488 /// getEndLoc - Get the location of the last token of this operand. 489 SMLoc getEndLoc() const { return EndLoc; } 490 491 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } 492 493 ARMCC::CondCodes getCondCode() const { 494 assert(Kind == k_CondCode && "Invalid access!"); 495 return CC.Val; 496 } 497 498 unsigned getCoproc() const { 499 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!"); 500 return Cop.Val; 501 } 502 503 StringRef getToken() const { 504 assert(Kind == k_Token && "Invalid access!"); 505 return StringRef(Tok.Data, Tok.Length); 506 } 507 508 unsigned getReg() const { 509 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!"); 510 return Reg.RegNum; 511 } 512 513 const SmallVectorImpl<unsigned> &getRegList() const { 514 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList || 515 Kind == k_SPRRegisterList) && "Invalid access!"); 516 return Registers; 517 } 518 519 const MCExpr *getImm() const { 520 assert(isImm() && "Invalid access!"); 521 return Imm.Val; 522 } 523 524 unsigned getVectorIndex() const { 525 assert(Kind == k_VectorIndex && "Invalid access!"); 526 return VectorIndex.Val; 527 } 528 529 ARM_MB::MemBOpt getMemBarrierOpt() const { 530 assert(Kind == k_MemBarrierOpt && "Invalid access!"); 531 return MBOpt.Val; 532 } 533 534 ARM_PROC::IFlags getProcIFlags() const { 535 assert(Kind == k_ProcIFlags && "Invalid access!"); 536 return IFlags.Val; 537 } 538 539 unsigned getMSRMask() const { 540 assert(Kind == k_MSRMask && "Invalid access!"); 541 return MMask.Val; 542 } 543 544 bool isCoprocNum() const { return Kind == k_CoprocNum; } 545 bool isCoprocReg() const { return Kind == k_CoprocReg; } 546 bool isCoprocOption() const { return Kind == k_CoprocOption; } 547 bool isCondCode() const { return Kind == k_CondCode; } 548 bool isCCOut() const { return Kind == k_CCOut; } 549 bool isITMask() const { return Kind == k_ITCondMask; } 550 bool isITCondCode() const { return Kind == k_CondCode; } 551 bool isImm() const { return Kind == k_Immediate; } 552 bool isFPImm() const { 553 if (!isImm()) return false; 554 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 555 if (!CE) return false; 556 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 557 return Val != -1; 558 } 559 bool isFBits16() const { 560 if (!isImm()) return false; 561 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 562 if (!CE) return false; 563 int64_t Value = CE->getValue(); 564 return Value >= 0 && Value <= 16; 565 } 566 bool isFBits32() const { 567 if (!isImm()) return false; 568 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 569 if (!CE) return false; 570 int64_t Value = CE->getValue(); 571 return Value >= 1 && Value <= 32; 572 } 573 bool isImm8s4() const { 574 if (!isImm()) return false; 575 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 576 if (!CE) return false; 577 int64_t Value = CE->getValue(); 578 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020; 579 } 580 bool isImm0_1020s4() const { 581 if (!isImm()) return false; 582 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 583 if (!CE) return false; 584 int64_t Value = CE->getValue(); 585 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020; 586 } 587 bool isImm0_508s4() const { 588 if (!isImm()) return false; 589 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 590 if (!CE) return false; 591 int64_t Value = CE->getValue(); 592 return ((Value & 3) == 0) && Value >= 0 && Value <= 508; 593 } 594 bool isImm0_508s4Neg() const { 595 if (!isImm()) return false; 596 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 597 if (!CE) return false; 598 int64_t Value = -CE->getValue(); 599 // explicitly exclude zero. we want that to use the normal 0_508 version. 600 return ((Value & 3) == 0) && Value > 0 && Value <= 508; 601 } 602 bool isImm0_255() const { 603 if (!isImm()) return false; 604 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 605 if (!CE) return false; 606 int64_t Value = CE->getValue(); 607 return Value >= 0 && Value < 256; 608 } 609 bool isImm0_4095() const { 610 if (!isImm()) return false; 611 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 612 if (!CE) return false; 613 int64_t Value = CE->getValue(); 614 return Value >= 0 && Value < 4096; 615 } 616 bool isImm0_4095Neg() const { 617 if (!isImm()) return false; 618 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 619 if (!CE) return false; 620 int64_t Value = -CE->getValue(); 621 return Value > 0 && Value < 4096; 622 } 623 bool isImm0_1() const { 624 if (!isImm()) return false; 625 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 626 if (!CE) return false; 627 int64_t Value = CE->getValue(); 628 return Value >= 0 && Value < 2; 629 } 630 bool isImm0_3() const { 631 if (!isImm()) return false; 632 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 633 if (!CE) return false; 634 int64_t Value = CE->getValue(); 635 return Value >= 0 && Value < 4; 636 } 637 bool isImm0_7() const { 638 if (!isImm()) return false; 639 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 640 if (!CE) return false; 641 int64_t Value = CE->getValue(); 642 return Value >= 0 && Value < 8; 643 } 644 bool isImm0_15() const { 645 if (!isImm()) return false; 646 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 647 if (!CE) return false; 648 int64_t Value = CE->getValue(); 649 return Value >= 0 && Value < 16; 650 } 651 bool isImm0_31() const { 652 if (!isImm()) return false; 653 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 654 if (!CE) return false; 655 int64_t Value = CE->getValue(); 656 return Value >= 0 && Value < 32; 657 } 658 bool isImm0_63() const { 659 if (!isImm()) return false; 660 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 661 if (!CE) return false; 662 int64_t Value = CE->getValue(); 663 return Value >= 0 && Value < 64; 664 } 665 bool isImm8() const { 666 if (!isImm()) return false; 667 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 668 if (!CE) return false; 669 int64_t Value = CE->getValue(); 670 return Value == 8; 671 } 672 bool isImm16() const { 673 if (!isImm()) return false; 674 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 675 if (!CE) return false; 676 int64_t Value = CE->getValue(); 677 return Value == 16; 678 } 679 bool isImm32() const { 680 if (!isImm()) return false; 681 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 682 if (!CE) return false; 683 int64_t Value = CE->getValue(); 684 return Value == 32; 685 } 686 bool isShrImm8() const { 687 if (!isImm()) return false; 688 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 689 if (!CE) return false; 690 int64_t Value = CE->getValue(); 691 return Value > 0 && Value <= 8; 692 } 693 bool isShrImm16() const { 694 if (!isImm()) return false; 695 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 696 if (!CE) return false; 697 int64_t Value = CE->getValue(); 698 return Value > 0 && Value <= 16; 699 } 700 bool isShrImm32() const { 701 if (!isImm()) return false; 702 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 703 if (!CE) return false; 704 int64_t Value = CE->getValue(); 705 return Value > 0 && Value <= 32; 706 } 707 bool isShrImm64() const { 708 if (!isImm()) return false; 709 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 710 if (!CE) return false; 711 int64_t Value = CE->getValue(); 712 return Value > 0 && Value <= 64; 713 } 714 bool isImm1_7() const { 715 if (!isImm()) return false; 716 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 717 if (!CE) return false; 718 int64_t Value = CE->getValue(); 719 return Value > 0 && Value < 8; 720 } 721 bool isImm1_15() const { 722 if (!isImm()) return false; 723 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 724 if (!CE) return false; 725 int64_t Value = CE->getValue(); 726 return Value > 0 && Value < 16; 727 } 728 bool isImm1_31() const { 729 if (!isImm()) return false; 730 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 731 if (!CE) return false; 732 int64_t Value = CE->getValue(); 733 return Value > 0 && Value < 32; 734 } 735 bool isImm1_16() const { 736 if (!isImm()) return false; 737 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 738 if (!CE) return false; 739 int64_t Value = CE->getValue(); 740 return Value > 0 && Value < 17; 741 } 742 bool isImm1_32() const { 743 if (!isImm()) return false; 744 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 745 if (!CE) return false; 746 int64_t Value = CE->getValue(); 747 return Value > 0 && Value < 33; 748 } 749 bool isImm0_32() const { 750 if (!isImm()) return false; 751 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 752 if (!CE) return false; 753 int64_t Value = CE->getValue(); 754 return Value >= 0 && Value < 33; 755 } 756 bool isImm0_65535() const { 757 if (!isImm()) return false; 758 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 759 if (!CE) return false; 760 int64_t Value = CE->getValue(); 761 return Value >= 0 && Value < 65536; 762 } 763 bool isImm0_65535Expr() const { 764 if (!isImm()) return false; 765 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 766 // If it's not a constant expression, it'll generate a fixup and be 767 // handled later. 768 if (!CE) return true; 769 int64_t Value = CE->getValue(); 770 return Value >= 0 && Value < 65536; 771 } 772 bool isImm24bit() const { 773 if (!isImm()) return false; 774 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 775 if (!CE) return false; 776 int64_t Value = CE->getValue(); 777 return Value >= 0 && Value <= 0xffffff; 778 } 779 bool isImmThumbSR() const { 780 if (!isImm()) return false; 781 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 782 if (!CE) return false; 783 int64_t Value = CE->getValue(); 784 return Value > 0 && Value < 33; 785 } 786 bool isPKHLSLImm() const { 787 if (!isImm()) return false; 788 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 789 if (!CE) return false; 790 int64_t Value = CE->getValue(); 791 return Value >= 0 && Value < 32; 792 } 793 bool isPKHASRImm() const { 794 if (!isImm()) return false; 795 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 796 if (!CE) return false; 797 int64_t Value = CE->getValue(); 798 return Value > 0 && Value <= 32; 799 } 800 bool isAdrLabel() const { 801 // If we have an immediate that's not a constant, treat it as a label 802 // reference needing a fixup. If it is a constant, but it can't fit 803 // into shift immediate encoding, we reject it. 804 if (isImm() && !isa<MCConstantExpr>(getImm())) return true; 805 else return (isARMSOImm() || isARMSOImmNeg()); 806 } 807 bool isARMSOImm() const { 808 if (!isImm()) return false; 809 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 810 if (!CE) return false; 811 int64_t Value = CE->getValue(); 812 return ARM_AM::getSOImmVal(Value) != -1; 813 } 814 bool isARMSOImmNot() const { 815 if (!isImm()) return false; 816 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 817 if (!CE) return false; 818 int64_t Value = CE->getValue(); 819 return ARM_AM::getSOImmVal(~Value) != -1; 820 } 821 bool isARMSOImmNeg() const { 822 if (!isImm()) return false; 823 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 824 if (!CE) return false; 825 int64_t Value = CE->getValue(); 826 // Only use this when not representable as a plain so_imm. 827 return ARM_AM::getSOImmVal(Value) == -1 && 828 ARM_AM::getSOImmVal(-Value) != -1; 829 } 830 bool isT2SOImm() const { 831 if (!isImm()) return false; 832 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 833 if (!CE) return false; 834 int64_t Value = CE->getValue(); 835 return ARM_AM::getT2SOImmVal(Value) != -1; 836 } 837 bool isT2SOImmNot() const { 838 if (!isImm()) return false; 839 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 840 if (!CE) return false; 841 int64_t Value = CE->getValue(); 842 return ARM_AM::getT2SOImmVal(~Value) != -1; 843 } 844 bool isT2SOImmNeg() const { 845 if (!isImm()) return false; 846 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 847 if (!CE) return false; 848 int64_t Value = CE->getValue(); 849 // Only use this when not representable as a plain so_imm. 850 return ARM_AM::getT2SOImmVal(Value) == -1 && 851 ARM_AM::getT2SOImmVal(-Value) != -1; 852 } 853 bool isSetEndImm() const { 854 if (!isImm()) return false; 855 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 856 if (!CE) return false; 857 int64_t Value = CE->getValue(); 858 return Value == 1 || Value == 0; 859 } 860 bool isReg() const { return Kind == k_Register; } 861 bool isRegList() const { return Kind == k_RegisterList; } 862 bool isDPRRegList() const { return Kind == k_DPRRegisterList; } 863 bool isSPRRegList() const { return Kind == k_SPRRegisterList; } 864 bool isToken() const { return Kind == k_Token; } 865 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; } 866 bool isMemory() const { return Kind == k_Memory; } 867 bool isShifterImm() const { return Kind == k_ShifterImmediate; } 868 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; } 869 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; } 870 bool isRotImm() const { return Kind == k_RotateImmediate; } 871 bool isBitfield() const { return Kind == k_BitfieldDescriptor; } 872 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; } 873 bool isPostIdxReg() const { 874 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; 875 } 876 bool isMemNoOffset(bool alignOK = false) const { 877 if (!isMemory()) 878 return false; 879 // No offset of any kind. 880 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 && 881 (alignOK || Memory.Alignment == 0); 882 } 883 bool isMemPCRelImm12() const { 884 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 885 return false; 886 // Base register must be PC. 887 if (Memory.BaseRegNum != ARM::PC) 888 return false; 889 // Immediate offset in range [-4095, 4095]. 890 if (!Memory.OffsetImm) return true; 891 int64_t Val = Memory.OffsetImm->getValue(); 892 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 893 } 894 bool isAlignedMemory() const { 895 return isMemNoOffset(true); 896 } 897 bool isAddrMode2() const { 898 if (!isMemory() || Memory.Alignment != 0) return false; 899 // Check for register offset. 900 if (Memory.OffsetRegNum) return true; 901 // Immediate offset in range [-4095, 4095]. 902 if (!Memory.OffsetImm) return true; 903 int64_t Val = Memory.OffsetImm->getValue(); 904 return Val > -4096 && Val < 4096; 905 } 906 bool isAM2OffsetImm() const { 907 if (!isImm()) return false; 908 // Immediate offset in range [-4095, 4095]. 909 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 910 if (!CE) return false; 911 int64_t Val = CE->getValue(); 912 return Val > -4096 && Val < 4096; 913 } 914 bool isAddrMode3() const { 915 // If we have an immediate that's not a constant, treat it as a label 916 // reference needing a fixup. If it is a constant, it's something else 917 // and we reject it. 918 if (isImm() && !isa<MCConstantExpr>(getImm())) 919 return true; 920 if (!isMemory() || Memory.Alignment != 0) return false; 921 // No shifts are legal for AM3. 922 if (Memory.ShiftType != ARM_AM::no_shift) return false; 923 // Check for register offset. 924 if (Memory.OffsetRegNum) return true; 925 // Immediate offset in range [-255, 255]. 926 if (!Memory.OffsetImm) return true; 927 int64_t Val = Memory.OffsetImm->getValue(); 928 // The #-0 offset is encoded as INT32_MIN, and we have to check 929 // for this too. 930 return (Val > -256 && Val < 256) || Val == INT32_MIN; 931 } 932 bool isAM3Offset() const { 933 if (Kind != k_Immediate && Kind != k_PostIndexRegister) 934 return false; 935 if (Kind == k_PostIndexRegister) 936 return PostIdxReg.ShiftTy == ARM_AM::no_shift; 937 // Immediate offset in range [-255, 255]. 938 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 939 if (!CE) return false; 940 int64_t Val = CE->getValue(); 941 // Special case, #-0 is INT32_MIN. 942 return (Val > -256 && Val < 256) || Val == INT32_MIN; 943 } 944 bool isAddrMode5() const { 945 // If we have an immediate that's not a constant, treat it as a label 946 // reference needing a fixup. If it is a constant, it's something else 947 // and we reject it. 948 if (isImm() && !isa<MCConstantExpr>(getImm())) 949 return true; 950 if (!isMemory() || Memory.Alignment != 0) return false; 951 // Check for register offset. 952 if (Memory.OffsetRegNum) return false; 953 // Immediate offset in range [-1020, 1020] and a multiple of 4. 954 if (!Memory.OffsetImm) return true; 955 int64_t Val = Memory.OffsetImm->getValue(); 956 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) || 957 Val == INT32_MIN; 958 } 959 bool isMemTBB() const { 960 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 961 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 962 return false; 963 return true; 964 } 965 bool isMemTBH() const { 966 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 967 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || 968 Memory.Alignment != 0 ) 969 return false; 970 return true; 971 } 972 bool isMemRegOffset() const { 973 if (!isMemory() || !Memory.OffsetRegNum || Memory.Alignment != 0) 974 return false; 975 return true; 976 } 977 bool isT2MemRegOffset() const { 978 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 979 Memory.Alignment != 0) 980 return false; 981 // Only lsl #{0, 1, 2, 3} allowed. 982 if (Memory.ShiftType == ARM_AM::no_shift) 983 return true; 984 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) 985 return false; 986 return true; 987 } 988 bool isMemThumbRR() const { 989 // Thumb reg+reg addressing is simple. Just two registers, a base and 990 // an offset. No shifts, negations or any other complicating factors. 991 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 992 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 993 return false; 994 return isARMLowRegister(Memory.BaseRegNum) && 995 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); 996 } 997 bool isMemThumbRIs4() const { 998 if (!isMemory() || Memory.OffsetRegNum != 0 || 999 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1000 return false; 1001 // Immediate offset, multiple of 4 in range [0, 124]. 1002 if (!Memory.OffsetImm) return true; 1003 int64_t Val = Memory.OffsetImm->getValue(); 1004 return Val >= 0 && Val <= 124 && (Val % 4) == 0; 1005 } 1006 bool isMemThumbRIs2() const { 1007 if (!isMemory() || Memory.OffsetRegNum != 0 || 1008 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1009 return false; 1010 // Immediate offset, multiple of 4 in range [0, 62]. 1011 if (!Memory.OffsetImm) return true; 1012 int64_t Val = Memory.OffsetImm->getValue(); 1013 return Val >= 0 && Val <= 62 && (Val % 2) == 0; 1014 } 1015 bool isMemThumbRIs1() const { 1016 if (!isMemory() || Memory.OffsetRegNum != 0 || 1017 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1018 return false; 1019 // Immediate offset in range [0, 31]. 1020 if (!Memory.OffsetImm) return true; 1021 int64_t Val = Memory.OffsetImm->getValue(); 1022 return Val >= 0 && Val <= 31; 1023 } 1024 bool isMemThumbSPI() const { 1025 if (!isMemory() || Memory.OffsetRegNum != 0 || 1026 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) 1027 return false; 1028 // Immediate offset, multiple of 4 in range [0, 1020]. 1029 if (!Memory.OffsetImm) return true; 1030 int64_t Val = Memory.OffsetImm->getValue(); 1031 return Val >= 0 && Val <= 1020 && (Val % 4) == 0; 1032 } 1033 bool isMemImm8s4Offset() const { 1034 // If we have an immediate that's not a constant, treat it as a label 1035 // reference needing a fixup. If it is a constant, it's something else 1036 // and we reject it. 1037 if (isImm() && !isa<MCConstantExpr>(getImm())) 1038 return true; 1039 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1040 return false; 1041 // Immediate offset a multiple of 4 in range [-1020, 1020]. 1042 if (!Memory.OffsetImm) return true; 1043 int64_t Val = Memory.OffsetImm->getValue(); 1044 // Special case, #-0 is INT32_MIN. 1045 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN; 1046 } 1047 bool isMemImm0_1020s4Offset() const { 1048 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1049 return false; 1050 // Immediate offset a multiple of 4 in range [0, 1020]. 1051 if (!Memory.OffsetImm) return true; 1052 int64_t Val = Memory.OffsetImm->getValue(); 1053 return Val >= 0 && Val <= 1020 && (Val & 3) == 0; 1054 } 1055 bool isMemImm8Offset() const { 1056 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1057 return false; 1058 // Base reg of PC isn't allowed for these encodings. 1059 if (Memory.BaseRegNum == ARM::PC) return false; 1060 // Immediate offset in range [-255, 255]. 1061 if (!Memory.OffsetImm) return true; 1062 int64_t Val = Memory.OffsetImm->getValue(); 1063 return (Val == INT32_MIN) || (Val > -256 && Val < 256); 1064 } 1065 bool isMemPosImm8Offset() const { 1066 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1067 return false; 1068 // Immediate offset in range [0, 255]. 1069 if (!Memory.OffsetImm) return true; 1070 int64_t Val = Memory.OffsetImm->getValue(); 1071 return Val >= 0 && Val < 256; 1072 } 1073 bool isMemNegImm8Offset() const { 1074 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1075 return false; 1076 // Base reg of PC isn't allowed for these encodings. 1077 if (Memory.BaseRegNum == ARM::PC) return false; 1078 // Immediate offset in range [-255, -1]. 1079 if (!Memory.OffsetImm) return false; 1080 int64_t Val = Memory.OffsetImm->getValue(); 1081 return (Val == INT32_MIN) || (Val > -256 && Val < 0); 1082 } 1083 bool isMemUImm12Offset() const { 1084 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1085 return false; 1086 // Immediate offset in range [0, 4095]. 1087 if (!Memory.OffsetImm) return true; 1088 int64_t Val = Memory.OffsetImm->getValue(); 1089 return (Val >= 0 && Val < 4096); 1090 } 1091 bool isMemImm12Offset() const { 1092 // If we have an immediate that's not a constant, treat it as a label 1093 // reference needing a fixup. If it is a constant, it's something else 1094 // and we reject it. 1095 if (isImm() && !isa<MCConstantExpr>(getImm())) 1096 return true; 1097 1098 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1099 return false; 1100 // Immediate offset in range [-4095, 4095]. 1101 if (!Memory.OffsetImm) return true; 1102 int64_t Val = Memory.OffsetImm->getValue(); 1103 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 1104 } 1105 bool isPostIdxImm8() const { 1106 if (!isImm()) return false; 1107 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1108 if (!CE) return false; 1109 int64_t Val = CE->getValue(); 1110 return (Val > -256 && Val < 256) || (Val == INT32_MIN); 1111 } 1112 bool isPostIdxImm8s4() const { 1113 if (!isImm()) return false; 1114 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1115 if (!CE) return false; 1116 int64_t Val = CE->getValue(); 1117 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) || 1118 (Val == INT32_MIN); 1119 } 1120 1121 bool isMSRMask() const { return Kind == k_MSRMask; } 1122 bool isProcIFlags() const { return Kind == k_ProcIFlags; } 1123 1124 // NEON operands. 1125 bool isSingleSpacedVectorList() const { 1126 return Kind == k_VectorList && !VectorList.isDoubleSpaced; 1127 } 1128 bool isDoubleSpacedVectorList() const { 1129 return Kind == k_VectorList && VectorList.isDoubleSpaced; 1130 } 1131 bool isVecListOneD() const { 1132 if (!isSingleSpacedVectorList()) return false; 1133 return VectorList.Count == 1; 1134 } 1135 1136 bool isVecListDPair() const { 1137 if (!isSingleSpacedVectorList()) return false; 1138 return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1139 .contains(VectorList.RegNum)); 1140 } 1141 1142 bool isVecListThreeD() const { 1143 if (!isSingleSpacedVectorList()) return false; 1144 return VectorList.Count == 3; 1145 } 1146 1147 bool isVecListFourD() const { 1148 if (!isSingleSpacedVectorList()) return false; 1149 return VectorList.Count == 4; 1150 } 1151 1152 bool isVecListDPairSpaced() const { 1153 if (isSingleSpacedVectorList()) return false; 1154 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] 1155 .contains(VectorList.RegNum)); 1156 } 1157 1158 bool isVecListThreeQ() const { 1159 if (!isDoubleSpacedVectorList()) return false; 1160 return VectorList.Count == 3; 1161 } 1162 1163 bool isVecListFourQ() const { 1164 if (!isDoubleSpacedVectorList()) return false; 1165 return VectorList.Count == 4; 1166 } 1167 1168 bool isSingleSpacedVectorAllLanes() const { 1169 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced; 1170 } 1171 bool isDoubleSpacedVectorAllLanes() const { 1172 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced; 1173 } 1174 bool isVecListOneDAllLanes() const { 1175 if (!isSingleSpacedVectorAllLanes()) return false; 1176 return VectorList.Count == 1; 1177 } 1178 1179 bool isVecListDPairAllLanes() const { 1180 if (!isSingleSpacedVectorAllLanes()) return false; 1181 return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1182 .contains(VectorList.RegNum)); 1183 } 1184 1185 bool isVecListDPairSpacedAllLanes() const { 1186 if (!isDoubleSpacedVectorAllLanes()) return false; 1187 return VectorList.Count == 2; 1188 } 1189 1190 bool isVecListThreeDAllLanes() const { 1191 if (!isSingleSpacedVectorAllLanes()) return false; 1192 return VectorList.Count == 3; 1193 } 1194 1195 bool isVecListThreeQAllLanes() const { 1196 if (!isDoubleSpacedVectorAllLanes()) return false; 1197 return VectorList.Count == 3; 1198 } 1199 1200 bool isVecListFourDAllLanes() const { 1201 if (!isSingleSpacedVectorAllLanes()) return false; 1202 return VectorList.Count == 4; 1203 } 1204 1205 bool isVecListFourQAllLanes() const { 1206 if (!isDoubleSpacedVectorAllLanes()) return false; 1207 return VectorList.Count == 4; 1208 } 1209 1210 bool isSingleSpacedVectorIndexed() const { 1211 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced; 1212 } 1213 bool isDoubleSpacedVectorIndexed() const { 1214 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced; 1215 } 1216 bool isVecListOneDByteIndexed() const { 1217 if (!isSingleSpacedVectorIndexed()) return false; 1218 return VectorList.Count == 1 && VectorList.LaneIndex <= 7; 1219 } 1220 1221 bool isVecListOneDHWordIndexed() const { 1222 if (!isSingleSpacedVectorIndexed()) return false; 1223 return VectorList.Count == 1 && VectorList.LaneIndex <= 3; 1224 } 1225 1226 bool isVecListOneDWordIndexed() const { 1227 if (!isSingleSpacedVectorIndexed()) return false; 1228 return VectorList.Count == 1 && VectorList.LaneIndex <= 1; 1229 } 1230 1231 bool isVecListTwoDByteIndexed() const { 1232 if (!isSingleSpacedVectorIndexed()) return false; 1233 return VectorList.Count == 2 && VectorList.LaneIndex <= 7; 1234 } 1235 1236 bool isVecListTwoDHWordIndexed() const { 1237 if (!isSingleSpacedVectorIndexed()) return false; 1238 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1239 } 1240 1241 bool isVecListTwoQWordIndexed() const { 1242 if (!isDoubleSpacedVectorIndexed()) return false; 1243 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1244 } 1245 1246 bool isVecListTwoQHWordIndexed() const { 1247 if (!isDoubleSpacedVectorIndexed()) return false; 1248 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1249 } 1250 1251 bool isVecListTwoDWordIndexed() const { 1252 if (!isSingleSpacedVectorIndexed()) return false; 1253 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1254 } 1255 1256 bool isVecListThreeDByteIndexed() const { 1257 if (!isSingleSpacedVectorIndexed()) return false; 1258 return VectorList.Count == 3 && VectorList.LaneIndex <= 7; 1259 } 1260 1261 bool isVecListThreeDHWordIndexed() const { 1262 if (!isSingleSpacedVectorIndexed()) return false; 1263 return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 1264 } 1265 1266 bool isVecListThreeQWordIndexed() const { 1267 if (!isDoubleSpacedVectorIndexed()) return false; 1268 return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 1269 } 1270 1271 bool isVecListThreeQHWordIndexed() const { 1272 if (!isDoubleSpacedVectorIndexed()) return false; 1273 return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 1274 } 1275 1276 bool isVecListThreeDWordIndexed() const { 1277 if (!isSingleSpacedVectorIndexed()) return false; 1278 return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 1279 } 1280 1281 bool isVecListFourDByteIndexed() const { 1282 if (!isSingleSpacedVectorIndexed()) return false; 1283 return VectorList.Count == 4 && VectorList.LaneIndex <= 7; 1284 } 1285 1286 bool isVecListFourDHWordIndexed() const { 1287 if (!isSingleSpacedVectorIndexed()) return false; 1288 return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 1289 } 1290 1291 bool isVecListFourQWordIndexed() const { 1292 if (!isDoubleSpacedVectorIndexed()) return false; 1293 return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 1294 } 1295 1296 bool isVecListFourQHWordIndexed() const { 1297 if (!isDoubleSpacedVectorIndexed()) return false; 1298 return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 1299 } 1300 1301 bool isVecListFourDWordIndexed() const { 1302 if (!isSingleSpacedVectorIndexed()) return false; 1303 return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 1304 } 1305 1306 bool isVectorIndex8() const { 1307 if (Kind != k_VectorIndex) return false; 1308 return VectorIndex.Val < 8; 1309 } 1310 bool isVectorIndex16() const { 1311 if (Kind != k_VectorIndex) return false; 1312 return VectorIndex.Val < 4; 1313 } 1314 bool isVectorIndex32() const { 1315 if (Kind != k_VectorIndex) return false; 1316 return VectorIndex.Val < 2; 1317 } 1318 1319 bool isNEONi8splat() const { 1320 if (!isImm()) return false; 1321 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1322 // Must be a constant. 1323 if (!CE) return false; 1324 int64_t Value = CE->getValue(); 1325 // i8 value splatted across 8 bytes. The immediate is just the 8 byte 1326 // value. 1327 return Value >= 0 && Value < 256; 1328 } 1329 1330 bool isNEONi16splat() const { 1331 if (!isImm()) return false; 1332 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1333 // Must be a constant. 1334 if (!CE) return false; 1335 int64_t Value = CE->getValue(); 1336 // i16 value in the range [0,255] or [0x0100, 0xff00] 1337 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00); 1338 } 1339 1340 bool isNEONi32splat() const { 1341 if (!isImm()) return false; 1342 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1343 // Must be a constant. 1344 if (!CE) return false; 1345 int64_t Value = CE->getValue(); 1346 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X. 1347 return (Value >= 0 && Value < 256) || 1348 (Value >= 0x0100 && Value <= 0xff00) || 1349 (Value >= 0x010000 && Value <= 0xff0000) || 1350 (Value >= 0x01000000 && Value <= 0xff000000); 1351 } 1352 1353 bool isNEONi32vmov() const { 1354 if (!isImm()) return false; 1355 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1356 // Must be a constant. 1357 if (!CE) return false; 1358 int64_t Value = CE->getValue(); 1359 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 1360 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 1361 return (Value >= 0 && Value < 256) || 1362 (Value >= 0x0100 && Value <= 0xff00) || 1363 (Value >= 0x010000 && Value <= 0xff0000) || 1364 (Value >= 0x01000000 && Value <= 0xff000000) || 1365 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 1366 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 1367 } 1368 bool isNEONi32vmovNeg() const { 1369 if (!isImm()) return false; 1370 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1371 // Must be a constant. 1372 if (!CE) return false; 1373 int64_t Value = ~CE->getValue(); 1374 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 1375 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 1376 return (Value >= 0 && Value < 256) || 1377 (Value >= 0x0100 && Value <= 0xff00) || 1378 (Value >= 0x010000 && Value <= 0xff0000) || 1379 (Value >= 0x01000000 && Value <= 0xff000000) || 1380 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 1381 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 1382 } 1383 1384 bool isNEONi64splat() const { 1385 if (!isImm()) return false; 1386 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1387 // Must be a constant. 1388 if (!CE) return false; 1389 uint64_t Value = CE->getValue(); 1390 // i64 value with each byte being either 0 or 0xff. 1391 for (unsigned i = 0; i < 8; ++i) 1392 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false; 1393 return true; 1394 } 1395 1396 void addExpr(MCInst &Inst, const MCExpr *Expr) const { 1397 // Add as immediates when possible. Null MCExpr = 0. 1398 if (Expr == 0) 1399 Inst.addOperand(MCOperand::CreateImm(0)); 1400 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) 1401 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1402 else 1403 Inst.addOperand(MCOperand::CreateExpr(Expr)); 1404 } 1405 1406 void addCondCodeOperands(MCInst &Inst, unsigned N) const { 1407 assert(N == 2 && "Invalid number of operands!"); 1408 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 1409 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; 1410 Inst.addOperand(MCOperand::CreateReg(RegNum)); 1411 } 1412 1413 void addCoprocNumOperands(MCInst &Inst, unsigned N) const { 1414 assert(N == 1 && "Invalid number of operands!"); 1415 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1416 } 1417 1418 void addCoprocRegOperands(MCInst &Inst, unsigned N) const { 1419 assert(N == 1 && "Invalid number of operands!"); 1420 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1421 } 1422 1423 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const { 1424 assert(N == 1 && "Invalid number of operands!"); 1425 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val)); 1426 } 1427 1428 void addITMaskOperands(MCInst &Inst, unsigned N) const { 1429 assert(N == 1 && "Invalid number of operands!"); 1430 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask)); 1431 } 1432 1433 void addITCondCodeOperands(MCInst &Inst, unsigned N) const { 1434 assert(N == 1 && "Invalid number of operands!"); 1435 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 1436 } 1437 1438 void addCCOutOperands(MCInst &Inst, unsigned N) const { 1439 assert(N == 1 && "Invalid number of operands!"); 1440 Inst.addOperand(MCOperand::CreateReg(getReg())); 1441 } 1442 1443 void addRegOperands(MCInst &Inst, unsigned N) const { 1444 assert(N == 1 && "Invalid number of operands!"); 1445 Inst.addOperand(MCOperand::CreateReg(getReg())); 1446 } 1447 1448 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { 1449 assert(N == 3 && "Invalid number of operands!"); 1450 assert(isRegShiftedReg() && 1451 "addRegShiftedRegOperands() on non RegShiftedReg!"); 1452 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg)); 1453 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); 1454 Inst.addOperand(MCOperand::CreateImm( 1455 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); 1456 } 1457 1458 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { 1459 assert(N == 2 && "Invalid number of operands!"); 1460 assert(isRegShiftedImm() && 1461 "addRegShiftedImmOperands() on non RegShiftedImm!"); 1462 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg)); 1463 // Shift of #32 is encoded as 0 where permitted 1464 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); 1465 Inst.addOperand(MCOperand::CreateImm( 1466 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); 1467 } 1468 1469 void addShifterImmOperands(MCInst &Inst, unsigned N) const { 1470 assert(N == 1 && "Invalid number of operands!"); 1471 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) | 1472 ShifterImm.Imm)); 1473 } 1474 1475 void addRegListOperands(MCInst &Inst, unsigned N) const { 1476 assert(N == 1 && "Invalid number of operands!"); 1477 const SmallVectorImpl<unsigned> &RegList = getRegList(); 1478 for (SmallVectorImpl<unsigned>::const_iterator 1479 I = RegList.begin(), E = RegList.end(); I != E; ++I) 1480 Inst.addOperand(MCOperand::CreateReg(*I)); 1481 } 1482 1483 void addDPRRegListOperands(MCInst &Inst, unsigned N) const { 1484 addRegListOperands(Inst, N); 1485 } 1486 1487 void addSPRRegListOperands(MCInst &Inst, unsigned N) const { 1488 addRegListOperands(Inst, N); 1489 } 1490 1491 void addRotImmOperands(MCInst &Inst, unsigned N) const { 1492 assert(N == 1 && "Invalid number of operands!"); 1493 // Encoded as val>>3. The printer handles display as 8, 16, 24. 1494 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3)); 1495 } 1496 1497 void addBitfieldOperands(MCInst &Inst, unsigned N) const { 1498 assert(N == 1 && "Invalid number of operands!"); 1499 // Munge the lsb/width into a bitfield mask. 1500 unsigned lsb = Bitfield.LSB; 1501 unsigned width = Bitfield.Width; 1502 // Make a 32-bit mask w/ the referenced bits clear and all other bits set. 1503 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> 1504 (32 - (lsb + width))); 1505 Inst.addOperand(MCOperand::CreateImm(Mask)); 1506 } 1507 1508 void addImmOperands(MCInst &Inst, unsigned N) const { 1509 assert(N == 1 && "Invalid number of operands!"); 1510 addExpr(Inst, getImm()); 1511 } 1512 1513 void addFBits16Operands(MCInst &Inst, unsigned N) const { 1514 assert(N == 1 && "Invalid number of operands!"); 1515 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1516 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue())); 1517 } 1518 1519 void addFBits32Operands(MCInst &Inst, unsigned N) const { 1520 assert(N == 1 && "Invalid number of operands!"); 1521 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1522 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue())); 1523 } 1524 1525 void addFPImmOperands(MCInst &Inst, unsigned N) const { 1526 assert(N == 1 && "Invalid number of operands!"); 1527 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1528 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 1529 Inst.addOperand(MCOperand::CreateImm(Val)); 1530 } 1531 1532 void addImm8s4Operands(MCInst &Inst, unsigned N) const { 1533 assert(N == 1 && "Invalid number of operands!"); 1534 // FIXME: We really want to scale the value here, but the LDRD/STRD 1535 // instruction don't encode operands that way yet. 1536 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1537 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1538 } 1539 1540 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { 1541 assert(N == 1 && "Invalid number of operands!"); 1542 // The immediate is scaled by four in the encoding and is stored 1543 // in the MCInst as such. Lop off the low two bits here. 1544 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1545 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 1546 } 1547 1548 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const { 1549 assert(N == 1 && "Invalid number of operands!"); 1550 // The immediate is scaled by four in the encoding and is stored 1551 // in the MCInst as such. Lop off the low two bits here. 1552 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1553 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4))); 1554 } 1555 1556 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const { 1557 assert(N == 1 && "Invalid number of operands!"); 1558 // The immediate is scaled by four in the encoding and is stored 1559 // in the MCInst as such. Lop off the low two bits here. 1560 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1561 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 1562 } 1563 1564 void addImm1_16Operands(MCInst &Inst, unsigned N) const { 1565 assert(N == 1 && "Invalid number of operands!"); 1566 // The constant encodes as the immediate-1, and we store in the instruction 1567 // the bits as encoded, so subtract off one here. 1568 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1569 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1570 } 1571 1572 void addImm1_32Operands(MCInst &Inst, unsigned N) const { 1573 assert(N == 1 && "Invalid number of operands!"); 1574 // The constant encodes as the immediate-1, and we store in the instruction 1575 // the bits as encoded, so subtract off one here. 1576 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1577 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1578 } 1579 1580 void addImmThumbSROperands(MCInst &Inst, unsigned N) const { 1581 assert(N == 1 && "Invalid number of operands!"); 1582 // The constant encodes as the immediate, except for 32, which encodes as 1583 // zero. 1584 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1585 unsigned Imm = CE->getValue(); 1586 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm))); 1587 } 1588 1589 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { 1590 assert(N == 1 && "Invalid number of operands!"); 1591 // An ASR value of 32 encodes as 0, so that's how we want to add it to 1592 // the instruction as well. 1593 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1594 int Val = CE->getValue(); 1595 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val)); 1596 } 1597 1598 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const { 1599 assert(N == 1 && "Invalid number of operands!"); 1600 // The operand is actually a t2_so_imm, but we have its bitwise 1601 // negation in the assembly source, so twiddle it here. 1602 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1603 Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1604 } 1605 1606 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const { 1607 assert(N == 1 && "Invalid number of operands!"); 1608 // The operand is actually a t2_so_imm, but we have its 1609 // negation in the assembly source, so twiddle it here. 1610 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1611 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1612 } 1613 1614 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const { 1615 assert(N == 1 && "Invalid number of operands!"); 1616 // The operand is actually an imm0_4095, but we have its 1617 // negation in the assembly source, so twiddle it here. 1618 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1619 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1620 } 1621 1622 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const { 1623 assert(N == 1 && "Invalid number of operands!"); 1624 // The operand is actually a so_imm, but we have its bitwise 1625 // negation in the assembly source, so twiddle it here. 1626 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1627 Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1628 } 1629 1630 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const { 1631 assert(N == 1 && "Invalid number of operands!"); 1632 // The operand is actually a so_imm, but we have its 1633 // negation in the assembly source, so twiddle it here. 1634 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1635 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1636 } 1637 1638 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { 1639 assert(N == 1 && "Invalid number of operands!"); 1640 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt()))); 1641 } 1642 1643 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { 1644 assert(N == 1 && "Invalid number of operands!"); 1645 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1646 } 1647 1648 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const { 1649 assert(N == 1 && "Invalid number of operands!"); 1650 int32_t Imm = Memory.OffsetImm->getValue(); 1651 // FIXME: Handle #-0 1652 if (Imm == INT32_MIN) Imm = 0; 1653 Inst.addOperand(MCOperand::CreateImm(Imm)); 1654 } 1655 1656 void addAdrLabelOperands(MCInst &Inst, unsigned N) const { 1657 assert(N == 1 && "Invalid number of operands!"); 1658 assert(isImm() && "Not an immediate!"); 1659 1660 // If we have an immediate that's not a constant, treat it as a label 1661 // reference needing a fixup. 1662 if (!isa<MCConstantExpr>(getImm())) { 1663 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1664 return; 1665 } 1666 1667 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1668 int Val = CE->getValue(); 1669 Inst.addOperand(MCOperand::CreateImm(Val)); 1670 } 1671 1672 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const { 1673 assert(N == 2 && "Invalid number of operands!"); 1674 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1675 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment)); 1676 } 1677 1678 void addAddrMode2Operands(MCInst &Inst, unsigned N) const { 1679 assert(N == 3 && "Invalid number of operands!"); 1680 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1681 if (!Memory.OffsetRegNum) { 1682 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1683 // Special case for #-0 1684 if (Val == INT32_MIN) Val = 0; 1685 if (Val < 0) Val = -Val; 1686 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1687 } else { 1688 // For register offset, we encode the shift type and negation flag 1689 // here. 1690 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 1691 Memory.ShiftImm, Memory.ShiftType); 1692 } 1693 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1694 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1695 Inst.addOperand(MCOperand::CreateImm(Val)); 1696 } 1697 1698 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { 1699 assert(N == 2 && "Invalid number of operands!"); 1700 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1701 assert(CE && "non-constant AM2OffsetImm operand!"); 1702 int32_t Val = CE->getValue(); 1703 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1704 // Special case for #-0 1705 if (Val == INT32_MIN) Val = 0; 1706 if (Val < 0) Val = -Val; 1707 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1708 Inst.addOperand(MCOperand::CreateReg(0)); 1709 Inst.addOperand(MCOperand::CreateImm(Val)); 1710 } 1711 1712 void addAddrMode3Operands(MCInst &Inst, unsigned N) const { 1713 assert(N == 3 && "Invalid number of operands!"); 1714 // If we have an immediate that's not a constant, treat it as a label 1715 // reference needing a fixup. If it is a constant, it's something else 1716 // and we reject it. 1717 if (isImm()) { 1718 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1719 Inst.addOperand(MCOperand::CreateReg(0)); 1720 Inst.addOperand(MCOperand::CreateImm(0)); 1721 return; 1722 } 1723 1724 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1725 if (!Memory.OffsetRegNum) { 1726 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1727 // Special case for #-0 1728 if (Val == INT32_MIN) Val = 0; 1729 if (Val < 0) Val = -Val; 1730 Val = ARM_AM::getAM3Opc(AddSub, Val); 1731 } else { 1732 // For register offset, we encode the shift type and negation flag 1733 // here. 1734 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0); 1735 } 1736 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1737 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1738 Inst.addOperand(MCOperand::CreateImm(Val)); 1739 } 1740 1741 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { 1742 assert(N == 2 && "Invalid number of operands!"); 1743 if (Kind == k_PostIndexRegister) { 1744 int32_t Val = 1745 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); 1746 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1747 Inst.addOperand(MCOperand::CreateImm(Val)); 1748 return; 1749 } 1750 1751 // Constant offset. 1752 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm()); 1753 int32_t Val = CE->getValue(); 1754 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1755 // Special case for #-0 1756 if (Val == INT32_MIN) Val = 0; 1757 if (Val < 0) Val = -Val; 1758 Val = ARM_AM::getAM3Opc(AddSub, Val); 1759 Inst.addOperand(MCOperand::CreateReg(0)); 1760 Inst.addOperand(MCOperand::CreateImm(Val)); 1761 } 1762 1763 void addAddrMode5Operands(MCInst &Inst, unsigned N) const { 1764 assert(N == 2 && "Invalid number of operands!"); 1765 // If we have an immediate that's not a constant, treat it as a label 1766 // reference needing a fixup. If it is a constant, it's something else 1767 // and we reject it. 1768 if (isImm()) { 1769 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1770 Inst.addOperand(MCOperand::CreateImm(0)); 1771 return; 1772 } 1773 1774 // The lower two bits are always zero and as such are not encoded. 1775 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 1776 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1777 // Special case for #-0 1778 if (Val == INT32_MIN) Val = 0; 1779 if (Val < 0) Val = -Val; 1780 Val = ARM_AM::getAM5Opc(AddSub, Val); 1781 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1782 Inst.addOperand(MCOperand::CreateImm(Val)); 1783 } 1784 1785 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const { 1786 assert(N == 2 && "Invalid number of operands!"); 1787 // If we have an immediate that's not a constant, treat it as a label 1788 // reference needing a fixup. If it is a constant, it's something else 1789 // and we reject it. 1790 if (isImm()) { 1791 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1792 Inst.addOperand(MCOperand::CreateImm(0)); 1793 return; 1794 } 1795 1796 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1797 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1798 Inst.addOperand(MCOperand::CreateImm(Val)); 1799 } 1800 1801 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const { 1802 assert(N == 2 && "Invalid number of operands!"); 1803 // The lower two bits are always zero and as such are not encoded. 1804 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 1805 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1806 Inst.addOperand(MCOperand::CreateImm(Val)); 1807 } 1808 1809 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1810 assert(N == 2 && "Invalid number of operands!"); 1811 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1812 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1813 Inst.addOperand(MCOperand::CreateImm(Val)); 1814 } 1815 1816 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1817 addMemImm8OffsetOperands(Inst, N); 1818 } 1819 1820 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1821 addMemImm8OffsetOperands(Inst, N); 1822 } 1823 1824 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { 1825 assert(N == 2 && "Invalid number of operands!"); 1826 // If this is an immediate, it's a label reference. 1827 if (isImm()) { 1828 addExpr(Inst, getImm()); 1829 Inst.addOperand(MCOperand::CreateImm(0)); 1830 return; 1831 } 1832 1833 // Otherwise, it's a normal memory reg+offset. 1834 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1835 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1836 Inst.addOperand(MCOperand::CreateImm(Val)); 1837 } 1838 1839 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { 1840 assert(N == 2 && "Invalid number of operands!"); 1841 // If this is an immediate, it's a label reference. 1842 if (isImm()) { 1843 addExpr(Inst, getImm()); 1844 Inst.addOperand(MCOperand::CreateImm(0)); 1845 return; 1846 } 1847 1848 // Otherwise, it's a normal memory reg+offset. 1849 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1850 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1851 Inst.addOperand(MCOperand::CreateImm(Val)); 1852 } 1853 1854 void addMemTBBOperands(MCInst &Inst, unsigned N) const { 1855 assert(N == 2 && "Invalid number of operands!"); 1856 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1857 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1858 } 1859 1860 void addMemTBHOperands(MCInst &Inst, unsigned N) const { 1861 assert(N == 2 && "Invalid number of operands!"); 1862 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1863 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1864 } 1865 1866 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { 1867 assert(N == 3 && "Invalid number of operands!"); 1868 unsigned Val = 1869 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 1870 Memory.ShiftImm, Memory.ShiftType); 1871 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1872 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1873 Inst.addOperand(MCOperand::CreateImm(Val)); 1874 } 1875 1876 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const { 1877 assert(N == 3 && "Invalid number of operands!"); 1878 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1879 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1880 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm)); 1881 } 1882 1883 void addMemThumbRROperands(MCInst &Inst, unsigned N) const { 1884 assert(N == 2 && "Invalid number of operands!"); 1885 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1886 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1887 } 1888 1889 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const { 1890 assert(N == 2 && "Invalid number of operands!"); 1891 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 1892 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1893 Inst.addOperand(MCOperand::CreateImm(Val)); 1894 } 1895 1896 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const { 1897 assert(N == 2 && "Invalid number of operands!"); 1898 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0; 1899 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1900 Inst.addOperand(MCOperand::CreateImm(Val)); 1901 } 1902 1903 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { 1904 assert(N == 2 && "Invalid number of operands!"); 1905 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0; 1906 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1907 Inst.addOperand(MCOperand::CreateImm(Val)); 1908 } 1909 1910 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { 1911 assert(N == 2 && "Invalid number of operands!"); 1912 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 1913 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1914 Inst.addOperand(MCOperand::CreateImm(Val)); 1915 } 1916 1917 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { 1918 assert(N == 1 && "Invalid number of operands!"); 1919 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1920 assert(CE && "non-constant post-idx-imm8 operand!"); 1921 int Imm = CE->getValue(); 1922 bool isAdd = Imm >= 0; 1923 if (Imm == INT32_MIN) Imm = 0; 1924 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; 1925 Inst.addOperand(MCOperand::CreateImm(Imm)); 1926 } 1927 1928 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const { 1929 assert(N == 1 && "Invalid number of operands!"); 1930 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1931 assert(CE && "non-constant post-idx-imm8s4 operand!"); 1932 int Imm = CE->getValue(); 1933 bool isAdd = Imm >= 0; 1934 if (Imm == INT32_MIN) Imm = 0; 1935 // Immediate is scaled by 4. 1936 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; 1937 Inst.addOperand(MCOperand::CreateImm(Imm)); 1938 } 1939 1940 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { 1941 assert(N == 2 && "Invalid number of operands!"); 1942 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1943 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd)); 1944 } 1945 1946 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { 1947 assert(N == 2 && "Invalid number of operands!"); 1948 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1949 // The sign, shift type, and shift amount are encoded in a single operand 1950 // using the AM2 encoding helpers. 1951 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; 1952 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, 1953 PostIdxReg.ShiftTy); 1954 Inst.addOperand(MCOperand::CreateImm(Imm)); 1955 } 1956 1957 void addMSRMaskOperands(MCInst &Inst, unsigned N) const { 1958 assert(N == 1 && "Invalid number of operands!"); 1959 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask()))); 1960 } 1961 1962 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { 1963 assert(N == 1 && "Invalid number of operands!"); 1964 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags()))); 1965 } 1966 1967 void addVecListOperands(MCInst &Inst, unsigned N) const { 1968 assert(N == 1 && "Invalid number of operands!"); 1969 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 1970 } 1971 1972 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const { 1973 assert(N == 2 && "Invalid number of operands!"); 1974 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 1975 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex)); 1976 } 1977 1978 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const { 1979 assert(N == 1 && "Invalid number of operands!"); 1980 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 1981 } 1982 1983 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const { 1984 assert(N == 1 && "Invalid number of operands!"); 1985 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 1986 } 1987 1988 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const { 1989 assert(N == 1 && "Invalid number of operands!"); 1990 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 1991 } 1992 1993 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const { 1994 assert(N == 1 && "Invalid number of operands!"); 1995 // The immediate encodes the type of constant as well as the value. 1996 // Mask in that this is an i8 splat. 1997 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1998 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00)); 1999 } 2000 2001 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const { 2002 assert(N == 1 && "Invalid number of operands!"); 2003 // The immediate encodes the type of constant as well as the value. 2004 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2005 unsigned Value = CE->getValue(); 2006 if (Value >= 256) 2007 Value = (Value >> 8) | 0xa00; 2008 else 2009 Value |= 0x800; 2010 Inst.addOperand(MCOperand::CreateImm(Value)); 2011 } 2012 2013 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const { 2014 assert(N == 1 && "Invalid number of operands!"); 2015 // The immediate encodes the type of constant as well as the value. 2016 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2017 unsigned Value = CE->getValue(); 2018 if (Value >= 256 && Value <= 0xff00) 2019 Value = (Value >> 8) | 0x200; 2020 else if (Value > 0xffff && Value <= 0xff0000) 2021 Value = (Value >> 16) | 0x400; 2022 else if (Value > 0xffffff) 2023 Value = (Value >> 24) | 0x600; 2024 Inst.addOperand(MCOperand::CreateImm(Value)); 2025 } 2026 2027 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const { 2028 assert(N == 1 && "Invalid number of operands!"); 2029 // The immediate encodes the type of constant as well as the value. 2030 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2031 unsigned Value = CE->getValue(); 2032 if (Value >= 256 && Value <= 0xffff) 2033 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 2034 else if (Value > 0xffff && Value <= 0xffffff) 2035 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 2036 else if (Value > 0xffffff) 2037 Value = (Value >> 24) | 0x600; 2038 Inst.addOperand(MCOperand::CreateImm(Value)); 2039 } 2040 2041 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const { 2042 assert(N == 1 && "Invalid number of operands!"); 2043 // The immediate encodes the type of constant as well as the value. 2044 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2045 unsigned Value = ~CE->getValue(); 2046 if (Value >= 256 && Value <= 0xffff) 2047 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 2048 else if (Value > 0xffff && Value <= 0xffffff) 2049 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 2050 else if (Value > 0xffffff) 2051 Value = (Value >> 24) | 0x600; 2052 Inst.addOperand(MCOperand::CreateImm(Value)); 2053 } 2054 2055 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const { 2056 assert(N == 1 && "Invalid number of operands!"); 2057 // The immediate encodes the type of constant as well as the value. 2058 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2059 uint64_t Value = CE->getValue(); 2060 unsigned Imm = 0; 2061 for (unsigned i = 0; i < 8; ++i, Value >>= 8) { 2062 Imm |= (Value & 1) << i; 2063 } 2064 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00)); 2065 } 2066 2067 virtual void print(raw_ostream &OS) const; 2068 2069 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) { 2070 ARMOperand *Op = new ARMOperand(k_ITCondMask); 2071 Op->ITMask.Mask = Mask; 2072 Op->StartLoc = S; 2073 Op->EndLoc = S; 2074 return Op; 2075 } 2076 2077 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) { 2078 ARMOperand *Op = new ARMOperand(k_CondCode); 2079 Op->CC.Val = CC; 2080 Op->StartLoc = S; 2081 Op->EndLoc = S; 2082 return Op; 2083 } 2084 2085 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) { 2086 ARMOperand *Op = new ARMOperand(k_CoprocNum); 2087 Op->Cop.Val = CopVal; 2088 Op->StartLoc = S; 2089 Op->EndLoc = S; 2090 return Op; 2091 } 2092 2093 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) { 2094 ARMOperand *Op = new ARMOperand(k_CoprocReg); 2095 Op->Cop.Val = CopVal; 2096 Op->StartLoc = S; 2097 Op->EndLoc = S; 2098 return Op; 2099 } 2100 2101 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) { 2102 ARMOperand *Op = new ARMOperand(k_CoprocOption); 2103 Op->Cop.Val = Val; 2104 Op->StartLoc = S; 2105 Op->EndLoc = E; 2106 return Op; 2107 } 2108 2109 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) { 2110 ARMOperand *Op = new ARMOperand(k_CCOut); 2111 Op->Reg.RegNum = RegNum; 2112 Op->StartLoc = S; 2113 Op->EndLoc = S; 2114 return Op; 2115 } 2116 2117 static ARMOperand *CreateToken(StringRef Str, SMLoc S) { 2118 ARMOperand *Op = new ARMOperand(k_Token); 2119 Op->Tok.Data = Str.data(); 2120 Op->Tok.Length = Str.size(); 2121 Op->StartLoc = S; 2122 Op->EndLoc = S; 2123 return Op; 2124 } 2125 2126 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { 2127 ARMOperand *Op = new ARMOperand(k_Register); 2128 Op->Reg.RegNum = RegNum; 2129 Op->StartLoc = S; 2130 Op->EndLoc = E; 2131 return Op; 2132 } 2133 2134 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, 2135 unsigned SrcReg, 2136 unsigned ShiftReg, 2137 unsigned ShiftImm, 2138 SMLoc S, SMLoc E) { 2139 ARMOperand *Op = new ARMOperand(k_ShiftedRegister); 2140 Op->RegShiftedReg.ShiftTy = ShTy; 2141 Op->RegShiftedReg.SrcReg = SrcReg; 2142 Op->RegShiftedReg.ShiftReg = ShiftReg; 2143 Op->RegShiftedReg.ShiftImm = ShiftImm; 2144 Op->StartLoc = S; 2145 Op->EndLoc = E; 2146 return Op; 2147 } 2148 2149 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, 2150 unsigned SrcReg, 2151 unsigned ShiftImm, 2152 SMLoc S, SMLoc E) { 2153 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate); 2154 Op->RegShiftedImm.ShiftTy = ShTy; 2155 Op->RegShiftedImm.SrcReg = SrcReg; 2156 Op->RegShiftedImm.ShiftImm = ShiftImm; 2157 Op->StartLoc = S; 2158 Op->EndLoc = E; 2159 return Op; 2160 } 2161 2162 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm, 2163 SMLoc S, SMLoc E) { 2164 ARMOperand *Op = new ARMOperand(k_ShifterImmediate); 2165 Op->ShifterImm.isASR = isASR; 2166 Op->ShifterImm.Imm = Imm; 2167 Op->StartLoc = S; 2168 Op->EndLoc = E; 2169 return Op; 2170 } 2171 2172 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) { 2173 ARMOperand *Op = new ARMOperand(k_RotateImmediate); 2174 Op->RotImm.Imm = Imm; 2175 Op->StartLoc = S; 2176 Op->EndLoc = E; 2177 return Op; 2178 } 2179 2180 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width, 2181 SMLoc S, SMLoc E) { 2182 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor); 2183 Op->Bitfield.LSB = LSB; 2184 Op->Bitfield.Width = Width; 2185 Op->StartLoc = S; 2186 Op->EndLoc = E; 2187 return Op; 2188 } 2189 2190 static ARMOperand * 2191 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs, 2192 SMLoc StartLoc, SMLoc EndLoc) { 2193 KindTy Kind = k_RegisterList; 2194 2195 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first)) 2196 Kind = k_DPRRegisterList; 2197 else if (ARMMCRegisterClasses[ARM::SPRRegClassID]. 2198 contains(Regs.front().first)) 2199 Kind = k_SPRRegisterList; 2200 2201 ARMOperand *Op = new ARMOperand(Kind); 2202 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator 2203 I = Regs.begin(), E = Regs.end(); I != E; ++I) 2204 Op->Registers.push_back(I->first); 2205 array_pod_sort(Op->Registers.begin(), Op->Registers.end()); 2206 Op->StartLoc = StartLoc; 2207 Op->EndLoc = EndLoc; 2208 return Op; 2209 } 2210 2211 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count, 2212 bool isDoubleSpaced, SMLoc S, SMLoc E) { 2213 ARMOperand *Op = new ARMOperand(k_VectorList); 2214 Op->VectorList.RegNum = RegNum; 2215 Op->VectorList.Count = Count; 2216 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2217 Op->StartLoc = S; 2218 Op->EndLoc = E; 2219 return Op; 2220 } 2221 2222 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count, 2223 bool isDoubleSpaced, 2224 SMLoc S, SMLoc E) { 2225 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes); 2226 Op->VectorList.RegNum = RegNum; 2227 Op->VectorList.Count = Count; 2228 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2229 Op->StartLoc = S; 2230 Op->EndLoc = E; 2231 return Op; 2232 } 2233 2234 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count, 2235 unsigned Index, 2236 bool isDoubleSpaced, 2237 SMLoc S, SMLoc E) { 2238 ARMOperand *Op = new ARMOperand(k_VectorListIndexed); 2239 Op->VectorList.RegNum = RegNum; 2240 Op->VectorList.Count = Count; 2241 Op->VectorList.LaneIndex = Index; 2242 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2243 Op->StartLoc = S; 2244 Op->EndLoc = E; 2245 return Op; 2246 } 2247 2248 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, 2249 MCContext &Ctx) { 2250 ARMOperand *Op = new ARMOperand(k_VectorIndex); 2251 Op->VectorIndex.Val = Idx; 2252 Op->StartLoc = S; 2253 Op->EndLoc = E; 2254 return Op; 2255 } 2256 2257 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) { 2258 ARMOperand *Op = new ARMOperand(k_Immediate); 2259 Op->Imm.Val = Val; 2260 Op->StartLoc = S; 2261 Op->EndLoc = E; 2262 return Op; 2263 } 2264 2265 static ARMOperand *CreateMem(unsigned BaseRegNum, 2266 const MCConstantExpr *OffsetImm, 2267 unsigned OffsetRegNum, 2268 ARM_AM::ShiftOpc ShiftType, 2269 unsigned ShiftImm, 2270 unsigned Alignment, 2271 bool isNegative, 2272 SMLoc S, SMLoc E) { 2273 ARMOperand *Op = new ARMOperand(k_Memory); 2274 Op->Memory.BaseRegNum = BaseRegNum; 2275 Op->Memory.OffsetImm = OffsetImm; 2276 Op->Memory.OffsetRegNum = OffsetRegNum; 2277 Op->Memory.ShiftType = ShiftType; 2278 Op->Memory.ShiftImm = ShiftImm; 2279 Op->Memory.Alignment = Alignment; 2280 Op->Memory.isNegative = isNegative; 2281 Op->StartLoc = S; 2282 Op->EndLoc = E; 2283 return Op; 2284 } 2285 2286 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd, 2287 ARM_AM::ShiftOpc ShiftTy, 2288 unsigned ShiftImm, 2289 SMLoc S, SMLoc E) { 2290 ARMOperand *Op = new ARMOperand(k_PostIndexRegister); 2291 Op->PostIdxReg.RegNum = RegNum; 2292 Op->PostIdxReg.isAdd = isAdd; 2293 Op->PostIdxReg.ShiftTy = ShiftTy; 2294 Op->PostIdxReg.ShiftImm = ShiftImm; 2295 Op->StartLoc = S; 2296 Op->EndLoc = E; 2297 return Op; 2298 } 2299 2300 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) { 2301 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt); 2302 Op->MBOpt.Val = Opt; 2303 Op->StartLoc = S; 2304 Op->EndLoc = S; 2305 return Op; 2306 } 2307 2308 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) { 2309 ARMOperand *Op = new ARMOperand(k_ProcIFlags); 2310 Op->IFlags.Val = IFlags; 2311 Op->StartLoc = S; 2312 Op->EndLoc = S; 2313 return Op; 2314 } 2315 2316 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) { 2317 ARMOperand *Op = new ARMOperand(k_MSRMask); 2318 Op->MMask.Val = MMask; 2319 Op->StartLoc = S; 2320 Op->EndLoc = S; 2321 return Op; 2322 } 2323 }; 2324 2325 } // end anonymous namespace. 2326 2327 void ARMOperand::print(raw_ostream &OS) const { 2328 switch (Kind) { 2329 case k_CondCode: 2330 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; 2331 break; 2332 case k_CCOut: 2333 OS << "<ccout " << getReg() << ">"; 2334 break; 2335 case k_ITCondMask: { 2336 static const char *const MaskStr[] = { 2337 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)", 2338 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)" 2339 }; 2340 assert((ITMask.Mask & 0xf) == ITMask.Mask); 2341 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">"; 2342 break; 2343 } 2344 case k_CoprocNum: 2345 OS << "<coprocessor number: " << getCoproc() << ">"; 2346 break; 2347 case k_CoprocReg: 2348 OS << "<coprocessor register: " << getCoproc() << ">"; 2349 break; 2350 case k_CoprocOption: 2351 OS << "<coprocessor option: " << CoprocOption.Val << ">"; 2352 break; 2353 case k_MSRMask: 2354 OS << "<mask: " << getMSRMask() << ">"; 2355 break; 2356 case k_Immediate: 2357 getImm()->print(OS); 2358 break; 2359 case k_MemBarrierOpt: 2360 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">"; 2361 break; 2362 case k_Memory: 2363 OS << "<memory " 2364 << " base:" << Memory.BaseRegNum; 2365 OS << ">"; 2366 break; 2367 case k_PostIndexRegister: 2368 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") 2369 << PostIdxReg.RegNum; 2370 if (PostIdxReg.ShiftTy != ARM_AM::no_shift) 2371 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " 2372 << PostIdxReg.ShiftImm; 2373 OS << ">"; 2374 break; 2375 case k_ProcIFlags: { 2376 OS << "<ARM_PROC::"; 2377 unsigned IFlags = getProcIFlags(); 2378 for (int i=2; i >= 0; --i) 2379 if (IFlags & (1 << i)) 2380 OS << ARM_PROC::IFlagsToString(1 << i); 2381 OS << ">"; 2382 break; 2383 } 2384 case k_Register: 2385 OS << "<register " << getReg() << ">"; 2386 break; 2387 case k_ShifterImmediate: 2388 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl") 2389 << " #" << ShifterImm.Imm << ">"; 2390 break; 2391 case k_ShiftedRegister: 2392 OS << "<so_reg_reg " 2393 << RegShiftedReg.SrcReg << " " 2394 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) 2395 << " " << RegShiftedReg.ShiftReg << ">"; 2396 break; 2397 case k_ShiftedImmediate: 2398 OS << "<so_reg_imm " 2399 << RegShiftedImm.SrcReg << " " 2400 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) 2401 << " #" << RegShiftedImm.ShiftImm << ">"; 2402 break; 2403 case k_RotateImmediate: 2404 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">"; 2405 break; 2406 case k_BitfieldDescriptor: 2407 OS << "<bitfield " << "lsb: " << Bitfield.LSB 2408 << ", width: " << Bitfield.Width << ">"; 2409 break; 2410 case k_RegisterList: 2411 case k_DPRRegisterList: 2412 case k_SPRRegisterList: { 2413 OS << "<register_list "; 2414 2415 const SmallVectorImpl<unsigned> &RegList = getRegList(); 2416 for (SmallVectorImpl<unsigned>::const_iterator 2417 I = RegList.begin(), E = RegList.end(); I != E; ) { 2418 OS << *I; 2419 if (++I < E) OS << ", "; 2420 } 2421 2422 OS << ">"; 2423 break; 2424 } 2425 case k_VectorList: 2426 OS << "<vector_list " << VectorList.Count << " * " 2427 << VectorList.RegNum << ">"; 2428 break; 2429 case k_VectorListAllLanes: 2430 OS << "<vector_list(all lanes) " << VectorList.Count << " * " 2431 << VectorList.RegNum << ">"; 2432 break; 2433 case k_VectorListIndexed: 2434 OS << "<vector_list(lane " << VectorList.LaneIndex << ") " 2435 << VectorList.Count << " * " << VectorList.RegNum << ">"; 2436 break; 2437 case k_Token: 2438 OS << "'" << getToken() << "'"; 2439 break; 2440 case k_VectorIndex: 2441 OS << "<vectorindex " << getVectorIndex() << ">"; 2442 break; 2443 } 2444 } 2445 2446 /// @name Auto-generated Match Functions 2447 /// { 2448 2449 static unsigned MatchRegisterName(StringRef Name); 2450 2451 /// } 2452 2453 bool ARMAsmParser::ParseRegister(unsigned &RegNo, 2454 SMLoc &StartLoc, SMLoc &EndLoc) { 2455 StartLoc = Parser.getTok().getLoc(); 2456 RegNo = tryParseRegister(); 2457 EndLoc = Parser.getTok().getLoc(); 2458 2459 return (RegNo == (unsigned)-1); 2460 } 2461 2462 /// Try to parse a register name. The token must be an Identifier when called, 2463 /// and if it is a register name the token is eaten and the register number is 2464 /// returned. Otherwise return -1. 2465 /// 2466 int ARMAsmParser::tryParseRegister() { 2467 const AsmToken &Tok = Parser.getTok(); 2468 if (Tok.isNot(AsmToken::Identifier)) return -1; 2469 2470 std::string lowerCase = Tok.getString().lower(); 2471 unsigned RegNum = MatchRegisterName(lowerCase); 2472 if (!RegNum) { 2473 RegNum = StringSwitch<unsigned>(lowerCase) 2474 .Case("r13", ARM::SP) 2475 .Case("r14", ARM::LR) 2476 .Case("r15", ARM::PC) 2477 .Case("ip", ARM::R12) 2478 // Additional register name aliases for 'gas' compatibility. 2479 .Case("a1", ARM::R0) 2480 .Case("a2", ARM::R1) 2481 .Case("a3", ARM::R2) 2482 .Case("a4", ARM::R3) 2483 .Case("v1", ARM::R4) 2484 .Case("v2", ARM::R5) 2485 .Case("v3", ARM::R6) 2486 .Case("v4", ARM::R7) 2487 .Case("v5", ARM::R8) 2488 .Case("v6", ARM::R9) 2489 .Case("v7", ARM::R10) 2490 .Case("v8", ARM::R11) 2491 .Case("sb", ARM::R9) 2492 .Case("sl", ARM::R10) 2493 .Case("fp", ARM::R11) 2494 .Default(0); 2495 } 2496 if (!RegNum) { 2497 // Check for aliases registered via .req. Canonicalize to lower case. 2498 // That's more consistent since register names are case insensitive, and 2499 // it's how the original entry was passed in from MC/MCParser/AsmParser. 2500 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase); 2501 // If no match, return failure. 2502 if (Entry == RegisterReqs.end()) 2503 return -1; 2504 Parser.Lex(); // Eat identifier token. 2505 return Entry->getValue(); 2506 } 2507 2508 Parser.Lex(); // Eat identifier token. 2509 2510 return RegNum; 2511 } 2512 2513 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0. 2514 // If a recoverable error occurs, return 1. If an irrecoverable error 2515 // occurs, return -1. An irrecoverable error is one where tokens have been 2516 // consumed in the process of trying to parse the shifter (i.e., when it is 2517 // indeed a shifter operand, but malformed). 2518 int ARMAsmParser::tryParseShiftRegister( 2519 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2520 SMLoc S = Parser.getTok().getLoc(); 2521 const AsmToken &Tok = Parser.getTok(); 2522 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 2523 2524 std::string lowerCase = Tok.getString().lower(); 2525 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) 2526 .Case("asl", ARM_AM::lsl) 2527 .Case("lsl", ARM_AM::lsl) 2528 .Case("lsr", ARM_AM::lsr) 2529 .Case("asr", ARM_AM::asr) 2530 .Case("ror", ARM_AM::ror) 2531 .Case("rrx", ARM_AM::rrx) 2532 .Default(ARM_AM::no_shift); 2533 2534 if (ShiftTy == ARM_AM::no_shift) 2535 return 1; 2536 2537 Parser.Lex(); // Eat the operator. 2538 2539 // The source register for the shift has already been added to the 2540 // operand list, so we need to pop it off and combine it into the shifted 2541 // register operand instead. 2542 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val()); 2543 if (!PrevOp->isReg()) 2544 return Error(PrevOp->getStartLoc(), "shift must be of a register"); 2545 int SrcReg = PrevOp->getReg(); 2546 int64_t Imm = 0; 2547 int ShiftReg = 0; 2548 if (ShiftTy == ARM_AM::rrx) { 2549 // RRX Doesn't have an explicit shift amount. The encoder expects 2550 // the shift register to be the same as the source register. Seems odd, 2551 // but OK. 2552 ShiftReg = SrcReg; 2553 } else { 2554 // Figure out if this is shifted by a constant or a register (for non-RRX). 2555 if (Parser.getTok().is(AsmToken::Hash) || 2556 Parser.getTok().is(AsmToken::Dollar)) { 2557 Parser.Lex(); // Eat hash. 2558 SMLoc ImmLoc = Parser.getTok().getLoc(); 2559 const MCExpr *ShiftExpr = 0; 2560 if (getParser().ParseExpression(ShiftExpr)) { 2561 Error(ImmLoc, "invalid immediate shift value"); 2562 return -1; 2563 } 2564 // The expression must be evaluatable as an immediate. 2565 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr); 2566 if (!CE) { 2567 Error(ImmLoc, "invalid immediate shift value"); 2568 return -1; 2569 } 2570 // Range check the immediate. 2571 // lsl, ror: 0 <= imm <= 31 2572 // lsr, asr: 0 <= imm <= 32 2573 Imm = CE->getValue(); 2574 if (Imm < 0 || 2575 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || 2576 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { 2577 Error(ImmLoc, "immediate shift value out of range"); 2578 return -1; 2579 } 2580 // shift by zero is a nop. Always send it through as lsl. 2581 // ('as' compatibility) 2582 if (Imm == 0) 2583 ShiftTy = ARM_AM::lsl; 2584 } else if (Parser.getTok().is(AsmToken::Identifier)) { 2585 ShiftReg = tryParseRegister(); 2586 SMLoc L = Parser.getTok().getLoc(); 2587 if (ShiftReg == -1) { 2588 Error (L, "expected immediate or register in shift operand"); 2589 return -1; 2590 } 2591 } else { 2592 Error (Parser.getTok().getLoc(), 2593 "expected immediate or register in shift operand"); 2594 return -1; 2595 } 2596 } 2597 2598 if (ShiftReg && ShiftTy != ARM_AM::rrx) 2599 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, 2600 ShiftReg, Imm, 2601 S, Parser.getTok().getLoc())); 2602 else 2603 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, 2604 S, Parser.getTok().getLoc())); 2605 2606 return 0; 2607 } 2608 2609 2610 /// Try to parse a register name. The token must be an Identifier when called. 2611 /// If it's a register, an AsmOperand is created. Another AsmOperand is created 2612 /// if there is a "writeback". 'true' if it's not a register. 2613 /// 2614 /// TODO this is likely to change to allow different register types and or to 2615 /// parse for a specific register type. 2616 bool ARMAsmParser:: 2617 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2618 SMLoc S = Parser.getTok().getLoc(); 2619 int RegNo = tryParseRegister(); 2620 if (RegNo == -1) 2621 return true; 2622 2623 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc())); 2624 2625 const AsmToken &ExclaimTok = Parser.getTok(); 2626 if (ExclaimTok.is(AsmToken::Exclaim)) { 2627 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), 2628 ExclaimTok.getLoc())); 2629 Parser.Lex(); // Eat exclaim token 2630 return false; 2631 } 2632 2633 // Also check for an index operand. This is only legal for vector registers, 2634 // but that'll get caught OK in operand matching, so we don't need to 2635 // explicitly filter everything else out here. 2636 if (Parser.getTok().is(AsmToken::LBrac)) { 2637 SMLoc SIdx = Parser.getTok().getLoc(); 2638 Parser.Lex(); // Eat left bracket token. 2639 2640 const MCExpr *ImmVal; 2641 if (getParser().ParseExpression(ImmVal)) 2642 return true; 2643 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal); 2644 if (!MCE) 2645 return TokError("immediate value expected for vector index"); 2646 2647 SMLoc E = Parser.getTok().getLoc(); 2648 if (Parser.getTok().isNot(AsmToken::RBrac)) 2649 return Error(E, "']' expected"); 2650 2651 Parser.Lex(); // Eat right bracket token. 2652 2653 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), 2654 SIdx, E, 2655 getContext())); 2656 } 2657 2658 return false; 2659 } 2660 2661 /// MatchCoprocessorOperandName - Try to parse an coprocessor related 2662 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3", 2663 /// "c5", ... 2664 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { 2665 // Use the same layout as the tablegen'erated register name matcher. Ugly, 2666 // but efficient. 2667 switch (Name.size()) { 2668 default: return -1; 2669 case 2: 2670 if (Name[0] != CoprocOp) 2671 return -1; 2672 switch (Name[1]) { 2673 default: return -1; 2674 case '0': return 0; 2675 case '1': return 1; 2676 case '2': return 2; 2677 case '3': return 3; 2678 case '4': return 4; 2679 case '5': return 5; 2680 case '6': return 6; 2681 case '7': return 7; 2682 case '8': return 8; 2683 case '9': return 9; 2684 } 2685 case 3: 2686 if (Name[0] != CoprocOp || Name[1] != '1') 2687 return -1; 2688 switch (Name[2]) { 2689 default: return -1; 2690 case '0': return 10; 2691 case '1': return 11; 2692 case '2': return 12; 2693 case '3': return 13; 2694 case '4': return 14; 2695 case '5': return 15; 2696 } 2697 } 2698 } 2699 2700 /// parseITCondCode - Try to parse a condition code for an IT instruction. 2701 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2702 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2703 SMLoc S = Parser.getTok().getLoc(); 2704 const AsmToken &Tok = Parser.getTok(); 2705 if (!Tok.is(AsmToken::Identifier)) 2706 return MatchOperand_NoMatch; 2707 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower()) 2708 .Case("eq", ARMCC::EQ) 2709 .Case("ne", ARMCC::NE) 2710 .Case("hs", ARMCC::HS) 2711 .Case("cs", ARMCC::HS) 2712 .Case("lo", ARMCC::LO) 2713 .Case("cc", ARMCC::LO) 2714 .Case("mi", ARMCC::MI) 2715 .Case("pl", ARMCC::PL) 2716 .Case("vs", ARMCC::VS) 2717 .Case("vc", ARMCC::VC) 2718 .Case("hi", ARMCC::HI) 2719 .Case("ls", ARMCC::LS) 2720 .Case("ge", ARMCC::GE) 2721 .Case("lt", ARMCC::LT) 2722 .Case("gt", ARMCC::GT) 2723 .Case("le", ARMCC::LE) 2724 .Case("al", ARMCC::AL) 2725 .Default(~0U); 2726 if (CC == ~0U) 2727 return MatchOperand_NoMatch; 2728 Parser.Lex(); // Eat the token. 2729 2730 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); 2731 2732 return MatchOperand_Success; 2733 } 2734 2735 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The 2736 /// token must be an Identifier when called, and if it is a coprocessor 2737 /// number, the token is eaten and the operand is added to the operand list. 2738 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2739 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2740 SMLoc S = Parser.getTok().getLoc(); 2741 const AsmToken &Tok = Parser.getTok(); 2742 if (Tok.isNot(AsmToken::Identifier)) 2743 return MatchOperand_NoMatch; 2744 2745 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p'); 2746 if (Num == -1) 2747 return MatchOperand_NoMatch; 2748 2749 Parser.Lex(); // Eat identifier token. 2750 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); 2751 return MatchOperand_Success; 2752 } 2753 2754 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The 2755 /// token must be an Identifier when called, and if it is a coprocessor 2756 /// number, the token is eaten and the operand is added to the operand list. 2757 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2758 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2759 SMLoc S = Parser.getTok().getLoc(); 2760 const AsmToken &Tok = Parser.getTok(); 2761 if (Tok.isNot(AsmToken::Identifier)) 2762 return MatchOperand_NoMatch; 2763 2764 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c'); 2765 if (Reg == -1) 2766 return MatchOperand_NoMatch; 2767 2768 Parser.Lex(); // Eat identifier token. 2769 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); 2770 return MatchOperand_Success; 2771 } 2772 2773 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand. 2774 /// coproc_option : '{' imm0_255 '}' 2775 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2776 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2777 SMLoc S = Parser.getTok().getLoc(); 2778 2779 // If this isn't a '{', this isn't a coprocessor immediate operand. 2780 if (Parser.getTok().isNot(AsmToken::LCurly)) 2781 return MatchOperand_NoMatch; 2782 Parser.Lex(); // Eat the '{' 2783 2784 const MCExpr *Expr; 2785 SMLoc Loc = Parser.getTok().getLoc(); 2786 if (getParser().ParseExpression(Expr)) { 2787 Error(Loc, "illegal expression"); 2788 return MatchOperand_ParseFail; 2789 } 2790 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 2791 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) { 2792 Error(Loc, "coprocessor option must be an immediate in range [0, 255]"); 2793 return MatchOperand_ParseFail; 2794 } 2795 int Val = CE->getValue(); 2796 2797 // Check for and consume the closing '}' 2798 if (Parser.getTok().isNot(AsmToken::RCurly)) 2799 return MatchOperand_ParseFail; 2800 SMLoc E = Parser.getTok().getLoc(); 2801 Parser.Lex(); // Eat the '}' 2802 2803 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); 2804 return MatchOperand_Success; 2805 } 2806 2807 // For register list parsing, we need to map from raw GPR register numbering 2808 // to the enumeration values. The enumeration values aren't sorted by 2809 // register number due to our using "sp", "lr" and "pc" as canonical names. 2810 static unsigned getNextRegister(unsigned Reg) { 2811 // If this is a GPR, we need to do it manually, otherwise we can rely 2812 // on the sort ordering of the enumeration since the other reg-classes 2813 // are sane. 2814 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 2815 return Reg + 1; 2816 switch(Reg) { 2817 default: llvm_unreachable("Invalid GPR number!"); 2818 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; 2819 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; 2820 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; 2821 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; 2822 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; 2823 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; 2824 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; 2825 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; 2826 } 2827 } 2828 2829 // Return the low-subreg of a given Q register. 2830 static unsigned getDRegFromQReg(unsigned QReg) { 2831 switch (QReg) { 2832 default: llvm_unreachable("expected a Q register!"); 2833 case ARM::Q0: return ARM::D0; 2834 case ARM::Q1: return ARM::D2; 2835 case ARM::Q2: return ARM::D4; 2836 case ARM::Q3: return ARM::D6; 2837 case ARM::Q4: return ARM::D8; 2838 case ARM::Q5: return ARM::D10; 2839 case ARM::Q6: return ARM::D12; 2840 case ARM::Q7: return ARM::D14; 2841 case ARM::Q8: return ARM::D16; 2842 case ARM::Q9: return ARM::D18; 2843 case ARM::Q10: return ARM::D20; 2844 case ARM::Q11: return ARM::D22; 2845 case ARM::Q12: return ARM::D24; 2846 case ARM::Q13: return ARM::D26; 2847 case ARM::Q14: return ARM::D28; 2848 case ARM::Q15: return ARM::D30; 2849 } 2850 } 2851 2852 /// Parse a register list. 2853 bool ARMAsmParser:: 2854 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2855 assert(Parser.getTok().is(AsmToken::LCurly) && 2856 "Token is not a Left Curly Brace"); 2857 SMLoc S = Parser.getTok().getLoc(); 2858 Parser.Lex(); // Eat '{' token. 2859 SMLoc RegLoc = Parser.getTok().getLoc(); 2860 2861 // Check the first register in the list to see what register class 2862 // this is a list of. 2863 int Reg = tryParseRegister(); 2864 if (Reg == -1) 2865 return Error(RegLoc, "register expected"); 2866 2867 // The reglist instructions have at most 16 registers, so reserve 2868 // space for that many. 2869 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers; 2870 2871 // Allow Q regs and just interpret them as the two D sub-registers. 2872 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 2873 Reg = getDRegFromQReg(Reg); 2874 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2875 ++Reg; 2876 } 2877 const MCRegisterClass *RC; 2878 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 2879 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; 2880 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) 2881 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; 2882 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) 2883 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; 2884 else 2885 return Error(RegLoc, "invalid register in register list"); 2886 2887 // Store the register. 2888 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2889 2890 // This starts immediately after the first register token in the list, 2891 // so we can see either a comma or a minus (range separator) as a legal 2892 // next token. 2893 while (Parser.getTok().is(AsmToken::Comma) || 2894 Parser.getTok().is(AsmToken::Minus)) { 2895 if (Parser.getTok().is(AsmToken::Minus)) { 2896 Parser.Lex(); // Eat the minus. 2897 SMLoc EndLoc = Parser.getTok().getLoc(); 2898 int EndReg = tryParseRegister(); 2899 if (EndReg == -1) 2900 return Error(EndLoc, "register expected"); 2901 // Allow Q regs and just interpret them as the two D sub-registers. 2902 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 2903 EndReg = getDRegFromQReg(EndReg) + 1; 2904 // If the register is the same as the start reg, there's nothing 2905 // more to do. 2906 if (Reg == EndReg) 2907 continue; 2908 // The register must be in the same register class as the first. 2909 if (!RC->contains(EndReg)) 2910 return Error(EndLoc, "invalid register in register list"); 2911 // Ranges must go from low to high. 2912 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg)) 2913 return Error(EndLoc, "bad range in register list"); 2914 2915 // Add all the registers in the range to the register list. 2916 while (Reg != EndReg) { 2917 Reg = getNextRegister(Reg); 2918 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2919 } 2920 continue; 2921 } 2922 Parser.Lex(); // Eat the comma. 2923 RegLoc = Parser.getTok().getLoc(); 2924 int OldReg = Reg; 2925 const AsmToken RegTok = Parser.getTok(); 2926 Reg = tryParseRegister(); 2927 if (Reg == -1) 2928 return Error(RegLoc, "register expected"); 2929 // Allow Q regs and just interpret them as the two D sub-registers. 2930 bool isQReg = false; 2931 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 2932 Reg = getDRegFromQReg(Reg); 2933 isQReg = true; 2934 } 2935 // The register must be in the same register class as the first. 2936 if (!RC->contains(Reg)) 2937 return Error(RegLoc, "invalid register in register list"); 2938 // List must be monotonically increasing. 2939 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) { 2940 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 2941 Warning(RegLoc, "register list not in ascending order"); 2942 else 2943 return Error(RegLoc, "register list not in ascending order"); 2944 } 2945 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) { 2946 Warning(RegLoc, "duplicated register (" + RegTok.getString() + 2947 ") in register list"); 2948 continue; 2949 } 2950 // VFP register lists must also be contiguous. 2951 // It's OK to use the enumeration values directly here rather, as the 2952 // VFP register classes have the enum sorted properly. 2953 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && 2954 Reg != OldReg + 1) 2955 return Error(RegLoc, "non-contiguous register range"); 2956 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2957 if (isQReg) 2958 Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc)); 2959 } 2960 2961 SMLoc E = Parser.getTok().getLoc(); 2962 if (Parser.getTok().isNot(AsmToken::RCurly)) 2963 return Error(E, "'}' expected"); 2964 Parser.Lex(); // Eat '}' token. 2965 2966 // Push the register list operand. 2967 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); 2968 2969 // The ARM system instruction variants for LDM/STM have a '^' token here. 2970 if (Parser.getTok().is(AsmToken::Caret)) { 2971 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc())); 2972 Parser.Lex(); // Eat '^' token. 2973 } 2974 2975 return false; 2976 } 2977 2978 // Helper function to parse the lane index for vector lists. 2979 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2980 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index) { 2981 Index = 0; // Always return a defined index value. 2982 if (Parser.getTok().is(AsmToken::LBrac)) { 2983 Parser.Lex(); // Eat the '['. 2984 if (Parser.getTok().is(AsmToken::RBrac)) { 2985 // "Dn[]" is the 'all lanes' syntax. 2986 LaneKind = AllLanes; 2987 Parser.Lex(); // Eat the ']'. 2988 return MatchOperand_Success; 2989 } 2990 2991 // There's an optional '#' token here. Normally there wouldn't be, but 2992 // inline assemble puts one in, and it's friendly to accept that. 2993 if (Parser.getTok().is(AsmToken::Hash)) 2994 Parser.Lex(); // Eat the '#' 2995 2996 const MCExpr *LaneIndex; 2997 SMLoc Loc = Parser.getTok().getLoc(); 2998 if (getParser().ParseExpression(LaneIndex)) { 2999 Error(Loc, "illegal expression"); 3000 return MatchOperand_ParseFail; 3001 } 3002 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex); 3003 if (!CE) { 3004 Error(Loc, "lane index must be empty or an integer"); 3005 return MatchOperand_ParseFail; 3006 } 3007 if (Parser.getTok().isNot(AsmToken::RBrac)) { 3008 Error(Parser.getTok().getLoc(), "']' expected"); 3009 return MatchOperand_ParseFail; 3010 } 3011 Parser.Lex(); // Eat the ']'. 3012 int64_t Val = CE->getValue(); 3013 3014 // FIXME: Make this range check context sensitive for .8, .16, .32. 3015 if (Val < 0 || Val > 7) { 3016 Error(Parser.getTok().getLoc(), "lane index out of range"); 3017 return MatchOperand_ParseFail; 3018 } 3019 Index = Val; 3020 LaneKind = IndexedLane; 3021 return MatchOperand_Success; 3022 } 3023 LaneKind = NoLanes; 3024 return MatchOperand_Success; 3025 } 3026 3027 // parse a vector register list 3028 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3029 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3030 VectorLaneTy LaneKind; 3031 unsigned LaneIndex; 3032 SMLoc S = Parser.getTok().getLoc(); 3033 // As an extension (to match gas), support a plain D register or Q register 3034 // (without encosing curly braces) as a single or double entry list, 3035 // respectively. 3036 if (Parser.getTok().is(AsmToken::Identifier)) { 3037 int Reg = tryParseRegister(); 3038 if (Reg == -1) 3039 return MatchOperand_NoMatch; 3040 SMLoc E = Parser.getTok().getLoc(); 3041 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { 3042 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex); 3043 if (Res != MatchOperand_Success) 3044 return Res; 3045 switch (LaneKind) { 3046 case NoLanes: 3047 E = Parser.getTok().getLoc(); 3048 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E)); 3049 break; 3050 case AllLanes: 3051 E = Parser.getTok().getLoc(); 3052 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, 3053 S, E)); 3054 break; 3055 case IndexedLane: 3056 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, 3057 LaneIndex, 3058 false, S, E)); 3059 break; 3060 } 3061 return MatchOperand_Success; 3062 } 3063 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3064 Reg = getDRegFromQReg(Reg); 3065 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex); 3066 if (Res != MatchOperand_Success) 3067 return Res; 3068 switch (LaneKind) { 3069 case NoLanes: 3070 E = Parser.getTok().getLoc(); 3071 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3072 &ARMMCRegisterClasses[ARM::DPairRegClassID]); 3073 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); 3074 break; 3075 case AllLanes: 3076 E = Parser.getTok().getLoc(); 3077 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3078 &ARMMCRegisterClasses[ARM::DPairRegClassID]); 3079 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, 3080 S, E)); 3081 break; 3082 case IndexedLane: 3083 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, 3084 LaneIndex, 3085 false, S, E)); 3086 break; 3087 } 3088 return MatchOperand_Success; 3089 } 3090 Error(S, "vector register expected"); 3091 return MatchOperand_ParseFail; 3092 } 3093 3094 if (Parser.getTok().isNot(AsmToken::LCurly)) 3095 return MatchOperand_NoMatch; 3096 3097 Parser.Lex(); // Eat '{' token. 3098 SMLoc RegLoc = Parser.getTok().getLoc(); 3099 3100 int Reg = tryParseRegister(); 3101 if (Reg == -1) { 3102 Error(RegLoc, "register expected"); 3103 return MatchOperand_ParseFail; 3104 } 3105 unsigned Count = 1; 3106 int Spacing = 0; 3107 unsigned FirstReg = Reg; 3108 // The list is of D registers, but we also allow Q regs and just interpret 3109 // them as the two D sub-registers. 3110 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3111 FirstReg = Reg = getDRegFromQReg(Reg); 3112 Spacing = 1; // double-spacing requires explicit D registers, otherwise 3113 // it's ambiguous with four-register single spaced. 3114 ++Reg; 3115 ++Count; 3116 } 3117 if (parseVectorLane(LaneKind, LaneIndex) != MatchOperand_Success) 3118 return MatchOperand_ParseFail; 3119 3120 while (Parser.getTok().is(AsmToken::Comma) || 3121 Parser.getTok().is(AsmToken::Minus)) { 3122 if (Parser.getTok().is(AsmToken::Minus)) { 3123 if (!Spacing) 3124 Spacing = 1; // Register range implies a single spaced list. 3125 else if (Spacing == 2) { 3126 Error(Parser.getTok().getLoc(), 3127 "sequential registers in double spaced list"); 3128 return MatchOperand_ParseFail; 3129 } 3130 Parser.Lex(); // Eat the minus. 3131 SMLoc EndLoc = Parser.getTok().getLoc(); 3132 int EndReg = tryParseRegister(); 3133 if (EndReg == -1) { 3134 Error(EndLoc, "register expected"); 3135 return MatchOperand_ParseFail; 3136 } 3137 // Allow Q regs and just interpret them as the two D sub-registers. 3138 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 3139 EndReg = getDRegFromQReg(EndReg) + 1; 3140 // If the register is the same as the start reg, there's nothing 3141 // more to do. 3142 if (Reg == EndReg) 3143 continue; 3144 // The register must be in the same register class as the first. 3145 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) { 3146 Error(EndLoc, "invalid register in register list"); 3147 return MatchOperand_ParseFail; 3148 } 3149 // Ranges must go from low to high. 3150 if (Reg > EndReg) { 3151 Error(EndLoc, "bad range in register list"); 3152 return MatchOperand_ParseFail; 3153 } 3154 // Parse the lane specifier if present. 3155 VectorLaneTy NextLaneKind; 3156 unsigned NextLaneIndex; 3157 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success) 3158 return MatchOperand_ParseFail; 3159 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3160 Error(EndLoc, "mismatched lane index in register list"); 3161 return MatchOperand_ParseFail; 3162 } 3163 EndLoc = Parser.getTok().getLoc(); 3164 3165 // Add all the registers in the range to the register list. 3166 Count += EndReg - Reg; 3167 Reg = EndReg; 3168 continue; 3169 } 3170 Parser.Lex(); // Eat the comma. 3171 RegLoc = Parser.getTok().getLoc(); 3172 int OldReg = Reg; 3173 Reg = tryParseRegister(); 3174 if (Reg == -1) { 3175 Error(RegLoc, "register expected"); 3176 return MatchOperand_ParseFail; 3177 } 3178 // vector register lists must be contiguous. 3179 // It's OK to use the enumeration values directly here rather, as the 3180 // VFP register classes have the enum sorted properly. 3181 // 3182 // The list is of D registers, but we also allow Q regs and just interpret 3183 // them as the two D sub-registers. 3184 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3185 if (!Spacing) 3186 Spacing = 1; // Register range implies a single spaced list. 3187 else if (Spacing == 2) { 3188 Error(RegLoc, 3189 "invalid register in double-spaced list (must be 'D' register')"); 3190 return MatchOperand_ParseFail; 3191 } 3192 Reg = getDRegFromQReg(Reg); 3193 if (Reg != OldReg + 1) { 3194 Error(RegLoc, "non-contiguous register range"); 3195 return MatchOperand_ParseFail; 3196 } 3197 ++Reg; 3198 Count += 2; 3199 // Parse the lane specifier if present. 3200 VectorLaneTy NextLaneKind; 3201 unsigned NextLaneIndex; 3202 SMLoc EndLoc = Parser.getTok().getLoc(); 3203 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success) 3204 return MatchOperand_ParseFail; 3205 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3206 Error(EndLoc, "mismatched lane index in register list"); 3207 return MatchOperand_ParseFail; 3208 } 3209 continue; 3210 } 3211 // Normal D register. 3212 // Figure out the register spacing (single or double) of the list if 3213 // we don't know it already. 3214 if (!Spacing) 3215 Spacing = 1 + (Reg == OldReg + 2); 3216 3217 // Just check that it's contiguous and keep going. 3218 if (Reg != OldReg + Spacing) { 3219 Error(RegLoc, "non-contiguous register range"); 3220 return MatchOperand_ParseFail; 3221 } 3222 ++Count; 3223 // Parse the lane specifier if present. 3224 VectorLaneTy NextLaneKind; 3225 unsigned NextLaneIndex; 3226 SMLoc EndLoc = Parser.getTok().getLoc(); 3227 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success) 3228 return MatchOperand_ParseFail; 3229 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3230 Error(EndLoc, "mismatched lane index in register list"); 3231 return MatchOperand_ParseFail; 3232 } 3233 } 3234 3235 SMLoc E = Parser.getTok().getLoc(); 3236 if (Parser.getTok().isNot(AsmToken::RCurly)) { 3237 Error(E, "'}' expected"); 3238 return MatchOperand_ParseFail; 3239 } 3240 Parser.Lex(); // Eat '}' token. 3241 3242 switch (LaneKind) { 3243 case NoLanes: 3244 // Two-register operands have been converted to the 3245 // composite register classes. 3246 if (Count == 2) { 3247 const MCRegisterClass *RC = (Spacing == 1) ? 3248 &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3249 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3250 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3251 } 3252 3253 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, 3254 (Spacing == 2), S, E)); 3255 break; 3256 case AllLanes: 3257 // Two-register operands have been converted to the 3258 // composite register classes. 3259 if (Count == 2) { 3260 const MCRegisterClass *RC = (Spacing == 1) ? 3261 &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3262 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3263 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3264 } 3265 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, 3266 (Spacing == 2), 3267 S, E)); 3268 break; 3269 case IndexedLane: 3270 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, 3271 LaneIndex, 3272 (Spacing == 2), 3273 S, E)); 3274 break; 3275 } 3276 return MatchOperand_Success; 3277 } 3278 3279 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. 3280 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3281 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3282 SMLoc S = Parser.getTok().getLoc(); 3283 const AsmToken &Tok = Parser.getTok(); 3284 unsigned Opt; 3285 3286 if (Tok.is(AsmToken::Identifier)) { 3287 StringRef OptStr = Tok.getString(); 3288 3289 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower()) 3290 .Case("sy", ARM_MB::SY) 3291 .Case("st", ARM_MB::ST) 3292 .Case("sh", ARM_MB::ISH) 3293 .Case("ish", ARM_MB::ISH) 3294 .Case("shst", ARM_MB::ISHST) 3295 .Case("ishst", ARM_MB::ISHST) 3296 .Case("nsh", ARM_MB::NSH) 3297 .Case("un", ARM_MB::NSH) 3298 .Case("nshst", ARM_MB::NSHST) 3299 .Case("unst", ARM_MB::NSHST) 3300 .Case("osh", ARM_MB::OSH) 3301 .Case("oshst", ARM_MB::OSHST) 3302 .Default(~0U); 3303 3304 if (Opt == ~0U) 3305 return MatchOperand_NoMatch; 3306 3307 Parser.Lex(); // Eat identifier token. 3308 } else if (Tok.is(AsmToken::Hash) || 3309 Tok.is(AsmToken::Dollar) || 3310 Tok.is(AsmToken::Integer)) { 3311 if (Parser.getTok().isNot(AsmToken::Integer)) 3312 Parser.Lex(); // Eat the '#'. 3313 SMLoc Loc = Parser.getTok().getLoc(); 3314 3315 const MCExpr *MemBarrierID; 3316 if (getParser().ParseExpression(MemBarrierID)) { 3317 Error(Loc, "illegal expression"); 3318 return MatchOperand_ParseFail; 3319 } 3320 3321 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID); 3322 if (!CE) { 3323 Error(Loc, "constant expression expected"); 3324 return MatchOperand_ParseFail; 3325 } 3326 3327 int Val = CE->getValue(); 3328 if (Val & ~0xf) { 3329 Error(Loc, "immediate value out of range"); 3330 return MatchOperand_ParseFail; 3331 } 3332 3333 Opt = ARM_MB::RESERVED_0 + Val; 3334 } else 3335 return MatchOperand_ParseFail; 3336 3337 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); 3338 return MatchOperand_Success; 3339 } 3340 3341 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. 3342 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3343 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3344 SMLoc S = Parser.getTok().getLoc(); 3345 const AsmToken &Tok = Parser.getTok(); 3346 if (!Tok.is(AsmToken::Identifier)) 3347 return MatchOperand_NoMatch; 3348 StringRef IFlagsStr = Tok.getString(); 3349 3350 // An iflags string of "none" is interpreted to mean that none of the AIF 3351 // bits are set. Not a terribly useful instruction, but a valid encoding. 3352 unsigned IFlags = 0; 3353 if (IFlagsStr != "none") { 3354 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { 3355 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1)) 3356 .Case("a", ARM_PROC::A) 3357 .Case("i", ARM_PROC::I) 3358 .Case("f", ARM_PROC::F) 3359 .Default(~0U); 3360 3361 // If some specific iflag is already set, it means that some letter is 3362 // present more than once, this is not acceptable. 3363 if (Flag == ~0U || (IFlags & Flag)) 3364 return MatchOperand_NoMatch; 3365 3366 IFlags |= Flag; 3367 } 3368 } 3369 3370 Parser.Lex(); // Eat identifier token. 3371 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); 3372 return MatchOperand_Success; 3373 } 3374 3375 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. 3376 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3377 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3378 SMLoc S = Parser.getTok().getLoc(); 3379 const AsmToken &Tok = Parser.getTok(); 3380 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 3381 StringRef Mask = Tok.getString(); 3382 3383 if (isMClass()) { 3384 // See ARMv6-M 10.1.1 3385 std::string Name = Mask.lower(); 3386 unsigned FlagsVal = StringSwitch<unsigned>(Name) 3387 // Note: in the documentation: 3388 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias 3389 // for MSR APSR_nzcvq. 3390 // but we do make it an alias here. This is so to get the "mask encoding" 3391 // bits correct on MSR APSR writes. 3392 // 3393 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers 3394 // should really only be allowed when writing a special register. Note 3395 // they get dropped in the MRS instruction reading a special register as 3396 // the SYSm field is only 8 bits. 3397 // 3398 // FIXME: the _g and _nzcvqg versions are only allowed if the processor 3399 // includes the DSP extension but that is not checked. 3400 .Case("apsr", 0x800) 3401 .Case("apsr_nzcvq", 0x800) 3402 .Case("apsr_g", 0x400) 3403 .Case("apsr_nzcvqg", 0xc00) 3404 .Case("iapsr", 0x801) 3405 .Case("iapsr_nzcvq", 0x801) 3406 .Case("iapsr_g", 0x401) 3407 .Case("iapsr_nzcvqg", 0xc01) 3408 .Case("eapsr", 0x802) 3409 .Case("eapsr_nzcvq", 0x802) 3410 .Case("eapsr_g", 0x402) 3411 .Case("eapsr_nzcvqg", 0xc02) 3412 .Case("xpsr", 0x803) 3413 .Case("xpsr_nzcvq", 0x803) 3414 .Case("xpsr_g", 0x403) 3415 .Case("xpsr_nzcvqg", 0xc03) 3416 .Case("ipsr", 0x805) 3417 .Case("epsr", 0x806) 3418 .Case("iepsr", 0x807) 3419 .Case("msp", 0x808) 3420 .Case("psp", 0x809) 3421 .Case("primask", 0x810) 3422 .Case("basepri", 0x811) 3423 .Case("basepri_max", 0x812) 3424 .Case("faultmask", 0x813) 3425 .Case("control", 0x814) 3426 .Default(~0U); 3427 3428 if (FlagsVal == ~0U) 3429 return MatchOperand_NoMatch; 3430 3431 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813) 3432 // basepri, basepri_max and faultmask only valid for V7m. 3433 return MatchOperand_NoMatch; 3434 3435 Parser.Lex(); // Eat identifier token. 3436 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3437 return MatchOperand_Success; 3438 } 3439 3440 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" 3441 size_t Start = 0, Next = Mask.find('_'); 3442 StringRef Flags = ""; 3443 std::string SpecReg = Mask.slice(Start, Next).lower(); 3444 if (Next != StringRef::npos) 3445 Flags = Mask.slice(Next+1, Mask.size()); 3446 3447 // FlagsVal contains the complete mask: 3448 // 3-0: Mask 3449 // 4: Special Reg (cpsr, apsr => 0; spsr => 1) 3450 unsigned FlagsVal = 0; 3451 3452 if (SpecReg == "apsr") { 3453 FlagsVal = StringSwitch<unsigned>(Flags) 3454 .Case("nzcvq", 0x8) // same as CPSR_f 3455 .Case("g", 0x4) // same as CPSR_s 3456 .Case("nzcvqg", 0xc) // same as CPSR_fs 3457 .Default(~0U); 3458 3459 if (FlagsVal == ~0U) { 3460 if (!Flags.empty()) 3461 return MatchOperand_NoMatch; 3462 else 3463 FlagsVal = 8; // No flag 3464 } 3465 } else if (SpecReg == "cpsr" || SpecReg == "spsr") { 3466 // cpsr_all is an alias for cpsr_fc, as is plain cpsr. 3467 if (Flags == "all" || Flags == "") 3468 Flags = "fc"; 3469 for (int i = 0, e = Flags.size(); i != e; ++i) { 3470 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1)) 3471 .Case("c", 1) 3472 .Case("x", 2) 3473 .Case("s", 4) 3474 .Case("f", 8) 3475 .Default(~0U); 3476 3477 // If some specific flag is already set, it means that some letter is 3478 // present more than once, this is not acceptable. 3479 if (FlagsVal == ~0U || (FlagsVal & Flag)) 3480 return MatchOperand_NoMatch; 3481 FlagsVal |= Flag; 3482 } 3483 } else // No match for special register. 3484 return MatchOperand_NoMatch; 3485 3486 // Special register without flags is NOT equivalent to "fc" flags. 3487 // NOTE: This is a divergence from gas' behavior. Uncommenting the following 3488 // two lines would enable gas compatibility at the expense of breaking 3489 // round-tripping. 3490 // 3491 // if (!FlagsVal) 3492 // FlagsVal = 0x9; 3493 3494 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) 3495 if (SpecReg == "spsr") 3496 FlagsVal |= 16; 3497 3498 Parser.Lex(); // Eat identifier token. 3499 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3500 return MatchOperand_Success; 3501 } 3502 3503 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3504 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op, 3505 int Low, int High) { 3506 const AsmToken &Tok = Parser.getTok(); 3507 if (Tok.isNot(AsmToken::Identifier)) { 3508 Error(Parser.getTok().getLoc(), Op + " operand expected."); 3509 return MatchOperand_ParseFail; 3510 } 3511 StringRef ShiftName = Tok.getString(); 3512 std::string LowerOp = Op.lower(); 3513 std::string UpperOp = Op.upper(); 3514 if (ShiftName != LowerOp && ShiftName != UpperOp) { 3515 Error(Parser.getTok().getLoc(), Op + " operand expected."); 3516 return MatchOperand_ParseFail; 3517 } 3518 Parser.Lex(); // Eat shift type token. 3519 3520 // There must be a '#' and a shift amount. 3521 if (Parser.getTok().isNot(AsmToken::Hash) && 3522 Parser.getTok().isNot(AsmToken::Dollar)) { 3523 Error(Parser.getTok().getLoc(), "'#' expected"); 3524 return MatchOperand_ParseFail; 3525 } 3526 Parser.Lex(); // Eat hash token. 3527 3528 const MCExpr *ShiftAmount; 3529 SMLoc Loc = Parser.getTok().getLoc(); 3530 if (getParser().ParseExpression(ShiftAmount)) { 3531 Error(Loc, "illegal expression"); 3532 return MatchOperand_ParseFail; 3533 } 3534 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3535 if (!CE) { 3536 Error(Loc, "constant expression expected"); 3537 return MatchOperand_ParseFail; 3538 } 3539 int Val = CE->getValue(); 3540 if (Val < Low || Val > High) { 3541 Error(Loc, "immediate value out of range"); 3542 return MatchOperand_ParseFail; 3543 } 3544 3545 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc())); 3546 3547 return MatchOperand_Success; 3548 } 3549 3550 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3551 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3552 const AsmToken &Tok = Parser.getTok(); 3553 SMLoc S = Tok.getLoc(); 3554 if (Tok.isNot(AsmToken::Identifier)) { 3555 Error(Tok.getLoc(), "'be' or 'le' operand expected"); 3556 return MatchOperand_ParseFail; 3557 } 3558 int Val = StringSwitch<int>(Tok.getString()) 3559 .Case("be", 1) 3560 .Case("le", 0) 3561 .Default(-1); 3562 Parser.Lex(); // Eat the token. 3563 3564 if (Val == -1) { 3565 Error(Tok.getLoc(), "'be' or 'le' operand expected"); 3566 return MatchOperand_ParseFail; 3567 } 3568 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val, 3569 getContext()), 3570 S, Parser.getTok().getLoc())); 3571 return MatchOperand_Success; 3572 } 3573 3574 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT 3575 /// instructions. Legal values are: 3576 /// lsl #n 'n' in [0,31] 3577 /// asr #n 'n' in [1,32] 3578 /// n == 32 encoded as n == 0. 3579 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3580 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3581 const AsmToken &Tok = Parser.getTok(); 3582 SMLoc S = Tok.getLoc(); 3583 if (Tok.isNot(AsmToken::Identifier)) { 3584 Error(S, "shift operator 'asr' or 'lsl' expected"); 3585 return MatchOperand_ParseFail; 3586 } 3587 StringRef ShiftName = Tok.getString(); 3588 bool isASR; 3589 if (ShiftName == "lsl" || ShiftName == "LSL") 3590 isASR = false; 3591 else if (ShiftName == "asr" || ShiftName == "ASR") 3592 isASR = true; 3593 else { 3594 Error(S, "shift operator 'asr' or 'lsl' expected"); 3595 return MatchOperand_ParseFail; 3596 } 3597 Parser.Lex(); // Eat the operator. 3598 3599 // A '#' and a shift amount. 3600 if (Parser.getTok().isNot(AsmToken::Hash) && 3601 Parser.getTok().isNot(AsmToken::Dollar)) { 3602 Error(Parser.getTok().getLoc(), "'#' expected"); 3603 return MatchOperand_ParseFail; 3604 } 3605 Parser.Lex(); // Eat hash token. 3606 3607 const MCExpr *ShiftAmount; 3608 SMLoc E = Parser.getTok().getLoc(); 3609 if (getParser().ParseExpression(ShiftAmount)) { 3610 Error(E, "malformed shift expression"); 3611 return MatchOperand_ParseFail; 3612 } 3613 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3614 if (!CE) { 3615 Error(E, "shift amount must be an immediate"); 3616 return MatchOperand_ParseFail; 3617 } 3618 3619 int64_t Val = CE->getValue(); 3620 if (isASR) { 3621 // Shift amount must be in [1,32] 3622 if (Val < 1 || Val > 32) { 3623 Error(E, "'asr' shift amount must be in range [1,32]"); 3624 return MatchOperand_ParseFail; 3625 } 3626 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode. 3627 if (isThumb() && Val == 32) { 3628 Error(E, "'asr #32' shift amount not allowed in Thumb mode"); 3629 return MatchOperand_ParseFail; 3630 } 3631 if (Val == 32) Val = 0; 3632 } else { 3633 // Shift amount must be in [1,32] 3634 if (Val < 0 || Val > 31) { 3635 Error(E, "'lsr' shift amount must be in range [0,31]"); 3636 return MatchOperand_ParseFail; 3637 } 3638 } 3639 3640 E = Parser.getTok().getLoc(); 3641 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E)); 3642 3643 return MatchOperand_Success; 3644 } 3645 3646 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family 3647 /// of instructions. Legal values are: 3648 /// ror #n 'n' in {0, 8, 16, 24} 3649 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3650 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3651 const AsmToken &Tok = Parser.getTok(); 3652 SMLoc S = Tok.getLoc(); 3653 if (Tok.isNot(AsmToken::Identifier)) 3654 return MatchOperand_NoMatch; 3655 StringRef ShiftName = Tok.getString(); 3656 if (ShiftName != "ror" && ShiftName != "ROR") 3657 return MatchOperand_NoMatch; 3658 Parser.Lex(); // Eat the operator. 3659 3660 // A '#' and a rotate amount. 3661 if (Parser.getTok().isNot(AsmToken::Hash) && 3662 Parser.getTok().isNot(AsmToken::Dollar)) { 3663 Error(Parser.getTok().getLoc(), "'#' expected"); 3664 return MatchOperand_ParseFail; 3665 } 3666 Parser.Lex(); // Eat hash token. 3667 3668 const MCExpr *ShiftAmount; 3669 SMLoc E = Parser.getTok().getLoc(); 3670 if (getParser().ParseExpression(ShiftAmount)) { 3671 Error(E, "malformed rotate expression"); 3672 return MatchOperand_ParseFail; 3673 } 3674 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3675 if (!CE) { 3676 Error(E, "rotate amount must be an immediate"); 3677 return MatchOperand_ParseFail; 3678 } 3679 3680 int64_t Val = CE->getValue(); 3681 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) 3682 // normally, zero is represented in asm by omitting the rotate operand 3683 // entirely. 3684 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { 3685 Error(E, "'ror' rotate amount must be 8, 16, or 24"); 3686 return MatchOperand_ParseFail; 3687 } 3688 3689 E = Parser.getTok().getLoc(); 3690 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E)); 3691 3692 return MatchOperand_Success; 3693 } 3694 3695 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3696 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3697 SMLoc S = Parser.getTok().getLoc(); 3698 // The bitfield descriptor is really two operands, the LSB and the width. 3699 if (Parser.getTok().isNot(AsmToken::Hash) && 3700 Parser.getTok().isNot(AsmToken::Dollar)) { 3701 Error(Parser.getTok().getLoc(), "'#' expected"); 3702 return MatchOperand_ParseFail; 3703 } 3704 Parser.Lex(); // Eat hash token. 3705 3706 const MCExpr *LSBExpr; 3707 SMLoc E = Parser.getTok().getLoc(); 3708 if (getParser().ParseExpression(LSBExpr)) { 3709 Error(E, "malformed immediate expression"); 3710 return MatchOperand_ParseFail; 3711 } 3712 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr); 3713 if (!CE) { 3714 Error(E, "'lsb' operand must be an immediate"); 3715 return MatchOperand_ParseFail; 3716 } 3717 3718 int64_t LSB = CE->getValue(); 3719 // The LSB must be in the range [0,31] 3720 if (LSB < 0 || LSB > 31) { 3721 Error(E, "'lsb' operand must be in the range [0,31]"); 3722 return MatchOperand_ParseFail; 3723 } 3724 E = Parser.getTok().getLoc(); 3725 3726 // Expect another immediate operand. 3727 if (Parser.getTok().isNot(AsmToken::Comma)) { 3728 Error(Parser.getTok().getLoc(), "too few operands"); 3729 return MatchOperand_ParseFail; 3730 } 3731 Parser.Lex(); // Eat hash token. 3732 if (Parser.getTok().isNot(AsmToken::Hash) && 3733 Parser.getTok().isNot(AsmToken::Dollar)) { 3734 Error(Parser.getTok().getLoc(), "'#' expected"); 3735 return MatchOperand_ParseFail; 3736 } 3737 Parser.Lex(); // Eat hash token. 3738 3739 const MCExpr *WidthExpr; 3740 if (getParser().ParseExpression(WidthExpr)) { 3741 Error(E, "malformed immediate expression"); 3742 return MatchOperand_ParseFail; 3743 } 3744 CE = dyn_cast<MCConstantExpr>(WidthExpr); 3745 if (!CE) { 3746 Error(E, "'width' operand must be an immediate"); 3747 return MatchOperand_ParseFail; 3748 } 3749 3750 int64_t Width = CE->getValue(); 3751 // The LSB must be in the range [1,32-lsb] 3752 if (Width < 1 || Width > 32 - LSB) { 3753 Error(E, "'width' operand must be in the range [1,32-lsb]"); 3754 return MatchOperand_ParseFail; 3755 } 3756 E = Parser.getTok().getLoc(); 3757 3758 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E)); 3759 3760 return MatchOperand_Success; 3761 } 3762 3763 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3764 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3765 // Check for a post-index addressing register operand. Specifically: 3766 // postidx_reg := '+' register {, shift} 3767 // | '-' register {, shift} 3768 // | register {, shift} 3769 3770 // This method must return MatchOperand_NoMatch without consuming any tokens 3771 // in the case where there is no match, as other alternatives take other 3772 // parse methods. 3773 AsmToken Tok = Parser.getTok(); 3774 SMLoc S = Tok.getLoc(); 3775 bool haveEaten = false; 3776 bool isAdd = true; 3777 int Reg = -1; 3778 if (Tok.is(AsmToken::Plus)) { 3779 Parser.Lex(); // Eat the '+' token. 3780 haveEaten = true; 3781 } else if (Tok.is(AsmToken::Minus)) { 3782 Parser.Lex(); // Eat the '-' token. 3783 isAdd = false; 3784 haveEaten = true; 3785 } 3786 if (Parser.getTok().is(AsmToken::Identifier)) 3787 Reg = tryParseRegister(); 3788 if (Reg == -1) { 3789 if (!haveEaten) 3790 return MatchOperand_NoMatch; 3791 Error(Parser.getTok().getLoc(), "register expected"); 3792 return MatchOperand_ParseFail; 3793 } 3794 SMLoc E = Parser.getTok().getLoc(); 3795 3796 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; 3797 unsigned ShiftImm = 0; 3798 if (Parser.getTok().is(AsmToken::Comma)) { 3799 Parser.Lex(); // Eat the ','. 3800 if (parseMemRegOffsetShift(ShiftTy, ShiftImm)) 3801 return MatchOperand_ParseFail; 3802 } 3803 3804 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, 3805 ShiftImm, S, E)); 3806 3807 return MatchOperand_Success; 3808 } 3809 3810 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3811 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3812 // Check for a post-index addressing register operand. Specifically: 3813 // am3offset := '+' register 3814 // | '-' register 3815 // | register 3816 // | # imm 3817 // | # + imm 3818 // | # - imm 3819 3820 // This method must return MatchOperand_NoMatch without consuming any tokens 3821 // in the case where there is no match, as other alternatives take other 3822 // parse methods. 3823 AsmToken Tok = Parser.getTok(); 3824 SMLoc S = Tok.getLoc(); 3825 3826 // Do immediates first, as we always parse those if we have a '#'. 3827 if (Parser.getTok().is(AsmToken::Hash) || 3828 Parser.getTok().is(AsmToken::Dollar)) { 3829 Parser.Lex(); // Eat the '#'. 3830 // Explicitly look for a '-', as we need to encode negative zero 3831 // differently. 3832 bool isNegative = Parser.getTok().is(AsmToken::Minus); 3833 const MCExpr *Offset; 3834 if (getParser().ParseExpression(Offset)) 3835 return MatchOperand_ParseFail; 3836 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 3837 if (!CE) { 3838 Error(S, "constant expression expected"); 3839 return MatchOperand_ParseFail; 3840 } 3841 SMLoc E = Tok.getLoc(); 3842 // Negative zero is encoded as the flag value INT32_MIN. 3843 int32_t Val = CE->getValue(); 3844 if (isNegative && Val == 0) 3845 Val = INT32_MIN; 3846 3847 Operands.push_back( 3848 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E)); 3849 3850 return MatchOperand_Success; 3851 } 3852 3853 3854 bool haveEaten = false; 3855 bool isAdd = true; 3856 int Reg = -1; 3857 if (Tok.is(AsmToken::Plus)) { 3858 Parser.Lex(); // Eat the '+' token. 3859 haveEaten = true; 3860 } else if (Tok.is(AsmToken::Minus)) { 3861 Parser.Lex(); // Eat the '-' token. 3862 isAdd = false; 3863 haveEaten = true; 3864 } 3865 if (Parser.getTok().is(AsmToken::Identifier)) 3866 Reg = tryParseRegister(); 3867 if (Reg == -1) { 3868 if (!haveEaten) 3869 return MatchOperand_NoMatch; 3870 Error(Parser.getTok().getLoc(), "register expected"); 3871 return MatchOperand_ParseFail; 3872 } 3873 SMLoc E = Parser.getTok().getLoc(); 3874 3875 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, 3876 0, S, E)); 3877 3878 return MatchOperand_Success; 3879 } 3880 3881 /// cvtT2LdrdPre - Convert parsed operands to MCInst. 3882 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3883 /// when they refer multiple MIOperands inside a single one. 3884 void ARMAsmParser:: 3885 cvtT2LdrdPre(MCInst &Inst, 3886 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3887 // Rt, Rt2 3888 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3889 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 3890 // Create a writeback register dummy placeholder. 3891 Inst.addOperand(MCOperand::CreateReg(0)); 3892 // addr 3893 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2); 3894 // pred 3895 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3896 } 3897 3898 /// cvtT2StrdPre - Convert parsed operands to MCInst. 3899 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3900 /// when they refer multiple MIOperands inside a single one. 3901 void ARMAsmParser:: 3902 cvtT2StrdPre(MCInst &Inst, 3903 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3904 // Create a writeback register dummy placeholder. 3905 Inst.addOperand(MCOperand::CreateReg(0)); 3906 // Rt, Rt2 3907 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3908 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 3909 // addr 3910 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2); 3911 // pred 3912 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3913 } 3914 3915 /// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst. 3916 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3917 /// when they refer multiple MIOperands inside a single one. 3918 void ARMAsmParser:: 3919 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, 3920 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3921 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3922 3923 // Create a writeback register dummy placeholder. 3924 Inst.addOperand(MCOperand::CreateImm(0)); 3925 3926 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2); 3927 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3928 } 3929 3930 /// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst. 3931 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3932 /// when they refer multiple MIOperands inside a single one. 3933 void ARMAsmParser:: 3934 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, 3935 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3936 // Create a writeback register dummy placeholder. 3937 Inst.addOperand(MCOperand::CreateImm(0)); 3938 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3939 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2); 3940 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3941 } 3942 3943 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 3944 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3945 /// when they refer multiple MIOperands inside a single one. 3946 void ARMAsmParser:: 3947 cvtLdWriteBackRegAddrMode2(MCInst &Inst, 3948 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3949 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3950 3951 // Create a writeback register dummy placeholder. 3952 Inst.addOperand(MCOperand::CreateImm(0)); 3953 3954 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 3955 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3956 } 3957 3958 /// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. 3959 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3960 /// when they refer multiple MIOperands inside a single one. 3961 void ARMAsmParser:: 3962 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, 3963 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3964 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3965 3966 // Create a writeback register dummy placeholder. 3967 Inst.addOperand(MCOperand::CreateImm(0)); 3968 3969 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); 3970 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3971 } 3972 3973 3974 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. 3975 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3976 /// when they refer multiple MIOperands inside a single one. 3977 void ARMAsmParser:: 3978 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, 3979 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3980 // Create a writeback register dummy placeholder. 3981 Inst.addOperand(MCOperand::CreateImm(0)); 3982 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3983 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); 3984 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3985 } 3986 3987 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 3988 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3989 /// when they refer multiple MIOperands inside a single one. 3990 void ARMAsmParser:: 3991 cvtStWriteBackRegAddrMode2(MCInst &Inst, 3992 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3993 // Create a writeback register dummy placeholder. 3994 Inst.addOperand(MCOperand::CreateImm(0)); 3995 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3996 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 3997 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3998 } 3999 4000 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 4001 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4002 /// when they refer multiple MIOperands inside a single one. 4003 void ARMAsmParser:: 4004 cvtStWriteBackRegAddrMode3(MCInst &Inst, 4005 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4006 // Create a writeback register dummy placeholder. 4007 Inst.addOperand(MCOperand::CreateImm(0)); 4008 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4009 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); 4010 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4011 } 4012 4013 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst. 4014 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4015 /// when they refer multiple MIOperands inside a single one. 4016 void ARMAsmParser:: 4017 cvtLdExtTWriteBackImm(MCInst &Inst, 4018 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4019 // Rt 4020 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4021 // Create a writeback register dummy placeholder. 4022 Inst.addOperand(MCOperand::CreateImm(0)); 4023 // addr 4024 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 4025 // offset 4026 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 4027 // pred 4028 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4029 } 4030 4031 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst. 4032 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4033 /// when they refer multiple MIOperands inside a single one. 4034 void ARMAsmParser:: 4035 cvtLdExtTWriteBackReg(MCInst &Inst, 4036 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4037 // Rt 4038 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4039 // Create a writeback register dummy placeholder. 4040 Inst.addOperand(MCOperand::CreateImm(0)); 4041 // addr 4042 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 4043 // offset 4044 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 4045 // pred 4046 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4047 } 4048 4049 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst. 4050 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4051 /// when they refer multiple MIOperands inside a single one. 4052 void ARMAsmParser:: 4053 cvtStExtTWriteBackImm(MCInst &Inst, 4054 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4055 // Create a writeback register dummy placeholder. 4056 Inst.addOperand(MCOperand::CreateImm(0)); 4057 // Rt 4058 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4059 // addr 4060 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 4061 // offset 4062 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 4063 // pred 4064 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4065 } 4066 4067 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst. 4068 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4069 /// when they refer multiple MIOperands inside a single one. 4070 void ARMAsmParser:: 4071 cvtStExtTWriteBackReg(MCInst &Inst, 4072 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4073 // Create a writeback register dummy placeholder. 4074 Inst.addOperand(MCOperand::CreateImm(0)); 4075 // Rt 4076 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4077 // addr 4078 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 4079 // offset 4080 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 4081 // pred 4082 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4083 } 4084 4085 /// cvtLdrdPre - Convert parsed operands to MCInst. 4086 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4087 /// when they refer multiple MIOperands inside a single one. 4088 void ARMAsmParser:: 4089 cvtLdrdPre(MCInst &Inst, 4090 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4091 // Rt, Rt2 4092 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4093 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 4094 // Create a writeback register dummy placeholder. 4095 Inst.addOperand(MCOperand::CreateImm(0)); 4096 // addr 4097 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 4098 // pred 4099 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4100 } 4101 4102 /// cvtStrdPre - Convert parsed operands to MCInst. 4103 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4104 /// when they refer multiple MIOperands inside a single one. 4105 void ARMAsmParser:: 4106 cvtStrdPre(MCInst &Inst, 4107 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4108 // Create a writeback register dummy placeholder. 4109 Inst.addOperand(MCOperand::CreateImm(0)); 4110 // Rt, Rt2 4111 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4112 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 4113 // addr 4114 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 4115 // pred 4116 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4117 } 4118 4119 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 4120 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4121 /// when they refer multiple MIOperands inside a single one. 4122 void ARMAsmParser:: 4123 cvtLdWriteBackRegAddrMode3(MCInst &Inst, 4124 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4125 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4126 // Create a writeback register dummy placeholder. 4127 Inst.addOperand(MCOperand::CreateImm(0)); 4128 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); 4129 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4130 } 4131 4132 /// cvtThumbMultiply - Convert parsed operands to MCInst. 4133 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4134 /// when they refer multiple MIOperands inside a single one. 4135 void ARMAsmParser:: 4136 cvtThumbMultiply(MCInst &Inst, 4137 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4138 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 4139 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1); 4140 // If we have a three-operand form, make sure to set Rn to be the operand 4141 // that isn't the same as Rd. 4142 unsigned RegOp = 4; 4143 if (Operands.size() == 6 && 4144 ((ARMOperand*)Operands[4])->getReg() == 4145 ((ARMOperand*)Operands[3])->getReg()) 4146 RegOp = 5; 4147 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1); 4148 Inst.addOperand(Inst.getOperand(0)); 4149 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2); 4150 } 4151 4152 void ARMAsmParser:: 4153 cvtVLDwbFixed(MCInst &Inst, 4154 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4155 // Vd 4156 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 4157 // Create a writeback register dummy placeholder. 4158 Inst.addOperand(MCOperand::CreateImm(0)); 4159 // Vn 4160 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 4161 // pred 4162 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4163 } 4164 4165 void ARMAsmParser:: 4166 cvtVLDwbRegister(MCInst &Inst, 4167 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4168 // Vd 4169 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 4170 // Create a writeback register dummy placeholder. 4171 Inst.addOperand(MCOperand::CreateImm(0)); 4172 // Vn 4173 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 4174 // Vm 4175 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1); 4176 // pred 4177 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4178 } 4179 4180 void ARMAsmParser:: 4181 cvtVSTwbFixed(MCInst &Inst, 4182 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4183 // Create a writeback register dummy placeholder. 4184 Inst.addOperand(MCOperand::CreateImm(0)); 4185 // Vn 4186 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 4187 // Vt 4188 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 4189 // pred 4190 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4191 } 4192 4193 void ARMAsmParser:: 4194 cvtVSTwbRegister(MCInst &Inst, 4195 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4196 // Create a writeback register dummy placeholder. 4197 Inst.addOperand(MCOperand::CreateImm(0)); 4198 // Vn 4199 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 4200 // Vm 4201 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1); 4202 // Vt 4203 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 4204 // pred 4205 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4206 } 4207 4208 /// Parse an ARM memory expression, return false if successful else return true 4209 /// or an error. The first token must be a '[' when called. 4210 bool ARMAsmParser:: 4211 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4212 SMLoc S, E; 4213 assert(Parser.getTok().is(AsmToken::LBrac) && 4214 "Token is not a Left Bracket"); 4215 S = Parser.getTok().getLoc(); 4216 Parser.Lex(); // Eat left bracket token. 4217 4218 const AsmToken &BaseRegTok = Parser.getTok(); 4219 int BaseRegNum = tryParseRegister(); 4220 if (BaseRegNum == -1) 4221 return Error(BaseRegTok.getLoc(), "register expected"); 4222 4223 // The next token must either be a comma or a closing bracket. 4224 const AsmToken &Tok = Parser.getTok(); 4225 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac)) 4226 return Error(Tok.getLoc(), "malformed memory operand"); 4227 4228 if (Tok.is(AsmToken::RBrac)) { 4229 E = Tok.getLoc(); 4230 Parser.Lex(); // Eat right bracket token. 4231 4232 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift, 4233 0, 0, false, S, E)); 4234 4235 // If there's a pre-indexing writeback marker, '!', just add it as a token 4236 // operand. It's rather odd, but syntactically valid. 4237 if (Parser.getTok().is(AsmToken::Exclaim)) { 4238 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4239 Parser.Lex(); // Eat the '!'. 4240 } 4241 4242 return false; 4243 } 4244 4245 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!"); 4246 Parser.Lex(); // Eat the comma. 4247 4248 // If we have a ':', it's an alignment specifier. 4249 if (Parser.getTok().is(AsmToken::Colon)) { 4250 Parser.Lex(); // Eat the ':'. 4251 E = Parser.getTok().getLoc(); 4252 4253 const MCExpr *Expr; 4254 if (getParser().ParseExpression(Expr)) 4255 return true; 4256 4257 // The expression has to be a constant. Memory references with relocations 4258 // don't come through here, as they use the <label> forms of the relevant 4259 // instructions. 4260 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 4261 if (!CE) 4262 return Error (E, "constant expression expected"); 4263 4264 unsigned Align = 0; 4265 switch (CE->getValue()) { 4266 default: 4267 return Error(E, 4268 "alignment specifier must be 16, 32, 64, 128, or 256 bits"); 4269 case 16: Align = 2; break; 4270 case 32: Align = 4; break; 4271 case 64: Align = 8; break; 4272 case 128: Align = 16; break; 4273 case 256: Align = 32; break; 4274 } 4275 4276 // Now we should have the closing ']' 4277 E = Parser.getTok().getLoc(); 4278 if (Parser.getTok().isNot(AsmToken::RBrac)) 4279 return Error(E, "']' expected"); 4280 Parser.Lex(); // Eat right bracket token. 4281 4282 // Don't worry about range checking the value here. That's handled by 4283 // the is*() predicates. 4284 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, 4285 ARM_AM::no_shift, 0, Align, 4286 false, S, E)); 4287 4288 // If there's a pre-indexing writeback marker, '!', just add it as a token 4289 // operand. 4290 if (Parser.getTok().is(AsmToken::Exclaim)) { 4291 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4292 Parser.Lex(); // Eat the '!'. 4293 } 4294 4295 return false; 4296 } 4297 4298 // If we have a '#', it's an immediate offset, else assume it's a register 4299 // offset. Be friendly and also accept a plain integer (without a leading 4300 // hash) for gas compatibility. 4301 if (Parser.getTok().is(AsmToken::Hash) || 4302 Parser.getTok().is(AsmToken::Dollar) || 4303 Parser.getTok().is(AsmToken::Integer)) { 4304 if (Parser.getTok().isNot(AsmToken::Integer)) 4305 Parser.Lex(); // Eat the '#'. 4306 E = Parser.getTok().getLoc(); 4307 4308 bool isNegative = getParser().getTok().is(AsmToken::Minus); 4309 const MCExpr *Offset; 4310 if (getParser().ParseExpression(Offset)) 4311 return true; 4312 4313 // The expression has to be a constant. Memory references with relocations 4314 // don't come through here, as they use the <label> forms of the relevant 4315 // instructions. 4316 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 4317 if (!CE) 4318 return Error (E, "constant expression expected"); 4319 4320 // If the constant was #-0, represent it as INT32_MIN. 4321 int32_t Val = CE->getValue(); 4322 if (isNegative && Val == 0) 4323 CE = MCConstantExpr::Create(INT32_MIN, getContext()); 4324 4325 // Now we should have the closing ']' 4326 E = Parser.getTok().getLoc(); 4327 if (Parser.getTok().isNot(AsmToken::RBrac)) 4328 return Error(E, "']' expected"); 4329 Parser.Lex(); // Eat right bracket token. 4330 4331 // Don't worry about range checking the value here. That's handled by 4332 // the is*() predicates. 4333 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0, 4334 ARM_AM::no_shift, 0, 0, 4335 false, S, E)); 4336 4337 // If there's a pre-indexing writeback marker, '!', just add it as a token 4338 // operand. 4339 if (Parser.getTok().is(AsmToken::Exclaim)) { 4340 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4341 Parser.Lex(); // Eat the '!'. 4342 } 4343 4344 return false; 4345 } 4346 4347 // The register offset is optionally preceded by a '+' or '-' 4348 bool isNegative = false; 4349 if (Parser.getTok().is(AsmToken::Minus)) { 4350 isNegative = true; 4351 Parser.Lex(); // Eat the '-'. 4352 } else if (Parser.getTok().is(AsmToken::Plus)) { 4353 // Nothing to do. 4354 Parser.Lex(); // Eat the '+'. 4355 } 4356 4357 E = Parser.getTok().getLoc(); 4358 int OffsetRegNum = tryParseRegister(); 4359 if (OffsetRegNum == -1) 4360 return Error(E, "register expected"); 4361 4362 // If there's a shift operator, handle it. 4363 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift; 4364 unsigned ShiftImm = 0; 4365 if (Parser.getTok().is(AsmToken::Comma)) { 4366 Parser.Lex(); // Eat the ','. 4367 if (parseMemRegOffsetShift(ShiftType, ShiftImm)) 4368 return true; 4369 } 4370 4371 // Now we should have the closing ']' 4372 E = Parser.getTok().getLoc(); 4373 if (Parser.getTok().isNot(AsmToken::RBrac)) 4374 return Error(E, "']' expected"); 4375 Parser.Lex(); // Eat right bracket token. 4376 4377 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum, 4378 ShiftType, ShiftImm, 0, isNegative, 4379 S, E)); 4380 4381 // If there's a pre-indexing writeback marker, '!', just add it as a token 4382 // operand. 4383 if (Parser.getTok().is(AsmToken::Exclaim)) { 4384 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4385 Parser.Lex(); // Eat the '!'. 4386 } 4387 4388 return false; 4389 } 4390 4391 /// parseMemRegOffsetShift - one of these two: 4392 /// ( lsl | lsr | asr | ror ) , # shift_amount 4393 /// rrx 4394 /// return true if it parses a shift otherwise it returns false. 4395 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St, 4396 unsigned &Amount) { 4397 SMLoc Loc = Parser.getTok().getLoc(); 4398 const AsmToken &Tok = Parser.getTok(); 4399 if (Tok.isNot(AsmToken::Identifier)) 4400 return true; 4401 StringRef ShiftName = Tok.getString(); 4402 if (ShiftName == "lsl" || ShiftName == "LSL" || 4403 ShiftName == "asl" || ShiftName == "ASL") 4404 St = ARM_AM::lsl; 4405 else if (ShiftName == "lsr" || ShiftName == "LSR") 4406 St = ARM_AM::lsr; 4407 else if (ShiftName == "asr" || ShiftName == "ASR") 4408 St = ARM_AM::asr; 4409 else if (ShiftName == "ror" || ShiftName == "ROR") 4410 St = ARM_AM::ror; 4411 else if (ShiftName == "rrx" || ShiftName == "RRX") 4412 St = ARM_AM::rrx; 4413 else 4414 return Error(Loc, "illegal shift operator"); 4415 Parser.Lex(); // Eat shift type token. 4416 4417 // rrx stands alone. 4418 Amount = 0; 4419 if (St != ARM_AM::rrx) { 4420 Loc = Parser.getTok().getLoc(); 4421 // A '#' and a shift amount. 4422 const AsmToken &HashTok = Parser.getTok(); 4423 if (HashTok.isNot(AsmToken::Hash) && 4424 HashTok.isNot(AsmToken::Dollar)) 4425 return Error(HashTok.getLoc(), "'#' expected"); 4426 Parser.Lex(); // Eat hash token. 4427 4428 const MCExpr *Expr; 4429 if (getParser().ParseExpression(Expr)) 4430 return true; 4431 // Range check the immediate. 4432 // lsl, ror: 0 <= imm <= 31 4433 // lsr, asr: 0 <= imm <= 32 4434 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 4435 if (!CE) 4436 return Error(Loc, "shift amount must be an immediate"); 4437 int64_t Imm = CE->getValue(); 4438 if (Imm < 0 || 4439 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) || 4440 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32)) 4441 return Error(Loc, "immediate shift value out of range"); 4442 Amount = Imm; 4443 } 4444 4445 return false; 4446 } 4447 4448 /// parseFPImm - A floating point immediate expression operand. 4449 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 4450 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4451 // Anything that can accept a floating point constant as an operand 4452 // needs to go through here, as the regular ParseExpression is 4453 // integer only. 4454 // 4455 // This routine still creates a generic Immediate operand, containing 4456 // a bitcast of the 64-bit floating point value. The various operands 4457 // that accept floats can check whether the value is valid for them 4458 // via the standard is*() predicates. 4459 4460 SMLoc S = Parser.getTok().getLoc(); 4461 4462 if (Parser.getTok().isNot(AsmToken::Hash) && 4463 Parser.getTok().isNot(AsmToken::Dollar)) 4464 return MatchOperand_NoMatch; 4465 4466 // Disambiguate the VMOV forms that can accept an FP immediate. 4467 // vmov.f32 <sreg>, #imm 4468 // vmov.f64 <dreg>, #imm 4469 // vmov.f32 <dreg>, #imm @ vector f32x2 4470 // vmov.f32 <qreg>, #imm @ vector f32x4 4471 // 4472 // There are also the NEON VMOV instructions which expect an 4473 // integer constant. Make sure we don't try to parse an FPImm 4474 // for these: 4475 // vmov.i{8|16|32|64} <dreg|qreg>, #imm 4476 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]); 4477 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" && 4478 TyOp->getToken() != ".f64")) 4479 return MatchOperand_NoMatch; 4480 4481 Parser.Lex(); // Eat the '#'. 4482 4483 // Handle negation, as that still comes through as a separate token. 4484 bool isNegative = false; 4485 if (Parser.getTok().is(AsmToken::Minus)) { 4486 isNegative = true; 4487 Parser.Lex(); 4488 } 4489 const AsmToken &Tok = Parser.getTok(); 4490 SMLoc Loc = Tok.getLoc(); 4491 if (Tok.is(AsmToken::Real)) { 4492 APFloat RealVal(APFloat::IEEEsingle, Tok.getString()); 4493 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue(); 4494 // If we had a '-' in front, toggle the sign bit. 4495 IntVal ^= (uint64_t)isNegative << 31; 4496 Parser.Lex(); // Eat the token. 4497 Operands.push_back(ARMOperand::CreateImm( 4498 MCConstantExpr::Create(IntVal, getContext()), 4499 S, Parser.getTok().getLoc())); 4500 return MatchOperand_Success; 4501 } 4502 // Also handle plain integers. Instructions which allow floating point 4503 // immediates also allow a raw encoded 8-bit value. 4504 if (Tok.is(AsmToken::Integer)) { 4505 int64_t Val = Tok.getIntVal(); 4506 Parser.Lex(); // Eat the token. 4507 if (Val > 255 || Val < 0) { 4508 Error(Loc, "encoded floating point value out of range"); 4509 return MatchOperand_ParseFail; 4510 } 4511 double RealVal = ARM_AM::getFPImmFloat(Val); 4512 Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue(); 4513 Operands.push_back(ARMOperand::CreateImm( 4514 MCConstantExpr::Create(Val, getContext()), S, 4515 Parser.getTok().getLoc())); 4516 return MatchOperand_Success; 4517 } 4518 4519 Error(Loc, "invalid floating point immediate"); 4520 return MatchOperand_ParseFail; 4521 } 4522 4523 /// Parse a arm instruction operand. For now this parses the operand regardless 4524 /// of the mnemonic. 4525 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, 4526 StringRef Mnemonic) { 4527 SMLoc S, E; 4528 4529 // Check if the current operand has a custom associated parser, if so, try to 4530 // custom parse the operand, or fallback to the general approach. 4531 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 4532 if (ResTy == MatchOperand_Success) 4533 return false; 4534 // If there wasn't a custom match, try the generic matcher below. Otherwise, 4535 // there was a match, but an error occurred, in which case, just return that 4536 // the operand parsing failed. 4537 if (ResTy == MatchOperand_ParseFail) 4538 return true; 4539 4540 switch (getLexer().getKind()) { 4541 default: 4542 Error(Parser.getTok().getLoc(), "unexpected token in operand"); 4543 return true; 4544 case AsmToken::Identifier: { 4545 if (!tryParseRegisterWithWriteBack(Operands)) 4546 return false; 4547 int Res = tryParseShiftRegister(Operands); 4548 if (Res == 0) // success 4549 return false; 4550 else if (Res == -1) // irrecoverable error 4551 return true; 4552 // If this is VMRS, check for the apsr_nzcv operand. 4553 if (Mnemonic == "vmrs" && 4554 Parser.getTok().getString().equals_lower("apsr_nzcv")) { 4555 S = Parser.getTok().getLoc(); 4556 Parser.Lex(); 4557 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S)); 4558 return false; 4559 } 4560 4561 // Fall though for the Identifier case that is not a register or a 4562 // special name. 4563 } 4564 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4) 4565 case AsmToken::Integer: // things like 1f and 2b as a branch targets 4566 case AsmToken::String: // quoted label names. 4567 case AsmToken::Dot: { // . as a branch target 4568 // This was not a register so parse other operands that start with an 4569 // identifier (like labels) as expressions and create them as immediates. 4570 const MCExpr *IdVal; 4571 S = Parser.getTok().getLoc(); 4572 if (getParser().ParseExpression(IdVal)) 4573 return true; 4574 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4575 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); 4576 return false; 4577 } 4578 case AsmToken::LBrac: 4579 return parseMemory(Operands); 4580 case AsmToken::LCurly: 4581 return parseRegisterList(Operands); 4582 case AsmToken::Dollar: 4583 case AsmToken::Hash: { 4584 // #42 -> immediate. 4585 S = Parser.getTok().getLoc(); 4586 Parser.Lex(); 4587 4588 if (Parser.getTok().isNot(AsmToken::Colon)) { 4589 bool isNegative = Parser.getTok().is(AsmToken::Minus); 4590 const MCExpr *ImmVal; 4591 if (getParser().ParseExpression(ImmVal)) 4592 return true; 4593 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal); 4594 if (CE) { 4595 int32_t Val = CE->getValue(); 4596 if (isNegative && Val == 0) 4597 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext()); 4598 } 4599 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4600 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); 4601 return false; 4602 } 4603 // w/ a ':' after the '#', it's just like a plain ':'. 4604 // FALLTHROUGH 4605 } 4606 case AsmToken::Colon: { 4607 // ":lower16:" and ":upper16:" expression prefixes 4608 // FIXME: Check it's an expression prefix, 4609 // e.g. (FOO - :lower16:BAR) isn't legal. 4610 ARMMCExpr::VariantKind RefKind; 4611 if (parsePrefix(RefKind)) 4612 return true; 4613 4614 const MCExpr *SubExprVal; 4615 if (getParser().ParseExpression(SubExprVal)) 4616 return true; 4617 4618 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal, 4619 getContext()); 4620 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4621 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); 4622 return false; 4623 } 4624 } 4625 } 4626 4627 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e. 4628 // :lower16: and :upper16:. 4629 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) { 4630 RefKind = ARMMCExpr::VK_ARM_None; 4631 4632 // :lower16: and :upper16: modifiers 4633 assert(getLexer().is(AsmToken::Colon) && "expected a :"); 4634 Parser.Lex(); // Eat ':' 4635 4636 if (getLexer().isNot(AsmToken::Identifier)) { 4637 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); 4638 return true; 4639 } 4640 4641 StringRef IDVal = Parser.getTok().getIdentifier(); 4642 if (IDVal == "lower16") { 4643 RefKind = ARMMCExpr::VK_ARM_LO16; 4644 } else if (IDVal == "upper16") { 4645 RefKind = ARMMCExpr::VK_ARM_HI16; 4646 } else { 4647 Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); 4648 return true; 4649 } 4650 Parser.Lex(); 4651 4652 if (getLexer().isNot(AsmToken::Colon)) { 4653 Error(Parser.getTok().getLoc(), "unexpected token after prefix"); 4654 return true; 4655 } 4656 Parser.Lex(); // Eat the last ':' 4657 return false; 4658 } 4659 4660 /// \brief Given a mnemonic, split out possible predication code and carry 4661 /// setting letters to form a canonical mnemonic and flags. 4662 // 4663 // FIXME: Would be nice to autogen this. 4664 // FIXME: This is a bit of a maze of special cases. 4665 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic, 4666 unsigned &PredicationCode, 4667 bool &CarrySetting, 4668 unsigned &ProcessorIMod, 4669 StringRef &ITMask) { 4670 PredicationCode = ARMCC::AL; 4671 CarrySetting = false; 4672 ProcessorIMod = 0; 4673 4674 // Ignore some mnemonics we know aren't predicated forms. 4675 // 4676 // FIXME: Would be nice to autogen this. 4677 if ((Mnemonic == "movs" && isThumb()) || 4678 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" || 4679 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || 4680 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" || 4681 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" || 4682 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" || 4683 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || 4684 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" || 4685 Mnemonic == "fmuls") 4686 return Mnemonic; 4687 4688 // First, split out any predication code. Ignore mnemonics we know aren't 4689 // predicated but do have a carry-set and so weren't caught above. 4690 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && 4691 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" && 4692 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" && 4693 Mnemonic != "sbcs" && Mnemonic != "rscs") { 4694 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2)) 4695 .Case("eq", ARMCC::EQ) 4696 .Case("ne", ARMCC::NE) 4697 .Case("hs", ARMCC::HS) 4698 .Case("cs", ARMCC::HS) 4699 .Case("lo", ARMCC::LO) 4700 .Case("cc", ARMCC::LO) 4701 .Case("mi", ARMCC::MI) 4702 .Case("pl", ARMCC::PL) 4703 .Case("vs", ARMCC::VS) 4704 .Case("vc", ARMCC::VC) 4705 .Case("hi", ARMCC::HI) 4706 .Case("ls", ARMCC::LS) 4707 .Case("ge", ARMCC::GE) 4708 .Case("lt", ARMCC::LT) 4709 .Case("gt", ARMCC::GT) 4710 .Case("le", ARMCC::LE) 4711 .Case("al", ARMCC::AL) 4712 .Default(~0U); 4713 if (CC != ~0U) { 4714 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2); 4715 PredicationCode = CC; 4716 } 4717 } 4718 4719 // Next, determine if we have a carry setting bit. We explicitly ignore all 4720 // the instructions we know end in 's'. 4721 if (Mnemonic.endswith("s") && 4722 !(Mnemonic == "cps" || Mnemonic == "mls" || 4723 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" || 4724 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" || 4725 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" || 4726 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" || 4727 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" || 4728 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" || 4729 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" || 4730 Mnemonic == "vfms" || Mnemonic == "vfnms" || 4731 (Mnemonic == "movs" && isThumb()))) { 4732 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); 4733 CarrySetting = true; 4734 } 4735 4736 // The "cps" instruction can have a interrupt mode operand which is glued into 4737 // the mnemonic. Check if this is the case, split it and parse the imod op 4738 if (Mnemonic.startswith("cps")) { 4739 // Split out any imod code. 4740 unsigned IMod = 4741 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2)) 4742 .Case("ie", ARM_PROC::IE) 4743 .Case("id", ARM_PROC::ID) 4744 .Default(~0U); 4745 if (IMod != ~0U) { 4746 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2); 4747 ProcessorIMod = IMod; 4748 } 4749 } 4750 4751 // The "it" instruction has the condition mask on the end of the mnemonic. 4752 if (Mnemonic.startswith("it")) { 4753 ITMask = Mnemonic.slice(2, Mnemonic.size()); 4754 Mnemonic = Mnemonic.slice(0, 2); 4755 } 4756 4757 return Mnemonic; 4758 } 4759 4760 /// \brief Given a canonical mnemonic, determine if the instruction ever allows 4761 /// inclusion of carry set or predication code operands. 4762 // 4763 // FIXME: It would be nice to autogen this. 4764 void ARMAsmParser:: 4765 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 4766 bool &CanAcceptPredicationCode) { 4767 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || 4768 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || 4769 Mnemonic == "add" || Mnemonic == "adc" || 4770 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" || 4771 Mnemonic == "orr" || Mnemonic == "mvn" || 4772 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || 4773 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" || 4774 Mnemonic == "vfm" || Mnemonic == "vfnm" || 4775 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" || 4776 Mnemonic == "mla" || Mnemonic == "smlal" || 4777 Mnemonic == "umlal" || Mnemonic == "umull"))) { 4778 CanAcceptCarrySet = true; 4779 } else 4780 CanAcceptCarrySet = false; 4781 4782 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" || 4783 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" || 4784 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" || 4785 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" || 4786 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" || 4787 (Mnemonic == "clrex" && !isThumb()) || 4788 (Mnemonic == "nop" && isThumbOne()) || 4789 ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" || 4790 Mnemonic == "ldc2" || Mnemonic == "ldc2l" || 4791 Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) || 4792 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) && 4793 !isThumb()) || 4794 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) { 4795 CanAcceptPredicationCode = false; 4796 } else 4797 CanAcceptPredicationCode = true; 4798 4799 if (isThumb()) { 4800 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" || 4801 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp") 4802 CanAcceptPredicationCode = false; 4803 } 4804 } 4805 4806 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic, 4807 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4808 // FIXME: This is all horribly hacky. We really need a better way to deal 4809 // with optional operands like this in the matcher table. 4810 4811 // The 'mov' mnemonic is special. One variant has a cc_out operand, while 4812 // another does not. Specifically, the MOVW instruction does not. So we 4813 // special case it here and remove the defaulted (non-setting) cc_out 4814 // operand if that's the instruction we're trying to match. 4815 // 4816 // We do this as post-processing of the explicit operands rather than just 4817 // conditionally adding the cc_out in the first place because we need 4818 // to check the type of the parsed immediate operand. 4819 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() && 4820 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() && 4821 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() && 4822 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 4823 return true; 4824 4825 // Register-register 'add' for thumb does not have a cc_out operand 4826 // when there are only two register operands. 4827 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && 4828 static_cast<ARMOperand*>(Operands[3])->isReg() && 4829 static_cast<ARMOperand*>(Operands[4])->isReg() && 4830 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 4831 return true; 4832 // Register-register 'add' for thumb does not have a cc_out operand 4833 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do 4834 // have to check the immediate range here since Thumb2 has a variant 4835 // that can handle a different range and has a cc_out operand. 4836 if (((isThumb() && Mnemonic == "add") || 4837 (isThumbTwo() && Mnemonic == "sub")) && 4838 Operands.size() == 6 && 4839 static_cast<ARMOperand*>(Operands[3])->isReg() && 4840 static_cast<ARMOperand*>(Operands[4])->isReg() && 4841 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP && 4842 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4843 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) || 4844 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4())) 4845 return true; 4846 // For Thumb2, add/sub immediate does not have a cc_out operand for the 4847 // imm0_4095 variant. That's the least-preferred variant when 4848 // selecting via the generic "add" mnemonic, so to know that we 4849 // should remove the cc_out operand, we have to explicitly check that 4850 // it's not one of the other variants. Ugh. 4851 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") && 4852 Operands.size() == 6 && 4853 static_cast<ARMOperand*>(Operands[3])->isReg() && 4854 static_cast<ARMOperand*>(Operands[4])->isReg() && 4855 static_cast<ARMOperand*>(Operands[5])->isImm()) { 4856 // Nest conditions rather than one big 'if' statement for readability. 4857 // 4858 // If either register is a high reg, it's either one of the SP 4859 // variants (handled above) or a 32-bit encoding, so we just 4860 // check against T3. If the second register is the PC, this is an 4861 // alternate form of ADR, which uses encoding T4, so check for that too. 4862 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 4863 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) && 4864 static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC && 4865 static_cast<ARMOperand*>(Operands[5])->isT2SOImm()) 4866 return false; 4867 // If both registers are low, we're in an IT block, and the immediate is 4868 // in range, we should use encoding T1 instead, which has a cc_out. 4869 if (inITBlock() && 4870 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) && 4871 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) && 4872 static_cast<ARMOperand*>(Operands[5])->isImm0_7()) 4873 return false; 4874 4875 // Otherwise, we use encoding T4, which does not have a cc_out 4876 // operand. 4877 return true; 4878 } 4879 4880 // The thumb2 multiply instruction doesn't have a CCOut register, so 4881 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to 4882 // use the 16-bit encoding or not. 4883 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 && 4884 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4885 static_cast<ARMOperand*>(Operands[3])->isReg() && 4886 static_cast<ARMOperand*>(Operands[4])->isReg() && 4887 static_cast<ARMOperand*>(Operands[5])->isReg() && 4888 // If the registers aren't low regs, the destination reg isn't the 4889 // same as one of the source regs, or the cc_out operand is zero 4890 // outside of an IT block, we have to use the 32-bit encoding, so 4891 // remove the cc_out operand. 4892 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 4893 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 4894 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) || 4895 !inITBlock() || 4896 (static_cast<ARMOperand*>(Operands[3])->getReg() != 4897 static_cast<ARMOperand*>(Operands[5])->getReg() && 4898 static_cast<ARMOperand*>(Operands[3])->getReg() != 4899 static_cast<ARMOperand*>(Operands[4])->getReg()))) 4900 return true; 4901 4902 // Also check the 'mul' syntax variant that doesn't specify an explicit 4903 // destination register. 4904 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 && 4905 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4906 static_cast<ARMOperand*>(Operands[3])->isReg() && 4907 static_cast<ARMOperand*>(Operands[4])->isReg() && 4908 // If the registers aren't low regs or the cc_out operand is zero 4909 // outside of an IT block, we have to use the 32-bit encoding, so 4910 // remove the cc_out operand. 4911 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 4912 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 4913 !inITBlock())) 4914 return true; 4915 4916 4917 4918 // Register-register 'add/sub' for thumb does not have a cc_out operand 4919 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also 4920 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't 4921 // right, this will result in better diagnostics (which operand is off) 4922 // anyway. 4923 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") && 4924 (Operands.size() == 5 || Operands.size() == 6) && 4925 static_cast<ARMOperand*>(Operands[3])->isReg() && 4926 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP && 4927 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4928 (static_cast<ARMOperand*>(Operands[4])->isImm() || 4929 (Operands.size() == 6 && 4930 static_cast<ARMOperand*>(Operands[5])->isImm()))) 4931 return true; 4932 4933 return false; 4934 } 4935 4936 static bool isDataTypeToken(StringRef Tok) { 4937 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" || 4938 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" || 4939 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" || 4940 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" || 4941 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" || 4942 Tok == ".f" || Tok == ".d"; 4943 } 4944 4945 // FIXME: This bit should probably be handled via an explicit match class 4946 // in the .td files that matches the suffix instead of having it be 4947 // a literal string token the way it is now. 4948 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) { 4949 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm"); 4950 } 4951 4952 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features); 4953 /// Parse an arm instruction mnemonic followed by its operands. 4954 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc, 4955 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4956 // Apply mnemonic aliases before doing anything else, as the destination 4957 // mnemnonic may include suffices and we want to handle them normally. 4958 // The generic tblgen'erated code does this later, at the start of 4959 // MatchInstructionImpl(), but that's too late for aliases that include 4960 // any sort of suffix. 4961 unsigned AvailableFeatures = getAvailableFeatures(); 4962 applyMnemonicAliases(Name, AvailableFeatures); 4963 4964 // First check for the ARM-specific .req directive. 4965 if (Parser.getTok().is(AsmToken::Identifier) && 4966 Parser.getTok().getIdentifier() == ".req") { 4967 parseDirectiveReq(Name, NameLoc); 4968 // We always return 'error' for this, as we're done with this 4969 // statement and don't need to match the 'instruction." 4970 return true; 4971 } 4972 4973 // Create the leading tokens for the mnemonic, split by '.' characters. 4974 size_t Start = 0, Next = Name.find('.'); 4975 StringRef Mnemonic = Name.slice(Start, Next); 4976 4977 // Split out the predication code and carry setting flag from the mnemonic. 4978 unsigned PredicationCode; 4979 unsigned ProcessorIMod; 4980 bool CarrySetting; 4981 StringRef ITMask; 4982 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting, 4983 ProcessorIMod, ITMask); 4984 4985 // In Thumb1, only the branch (B) instruction can be predicated. 4986 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") { 4987 Parser.EatToEndOfStatement(); 4988 return Error(NameLoc, "conditional execution not supported in Thumb1"); 4989 } 4990 4991 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); 4992 4993 // Handle the IT instruction ITMask. Convert it to a bitmask. This 4994 // is the mask as it will be for the IT encoding if the conditional 4995 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case 4996 // where the conditional bit0 is zero, the instruction post-processing 4997 // will adjust the mask accordingly. 4998 if (Mnemonic == "it") { 4999 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2); 5000 if (ITMask.size() > 3) { 5001 Parser.EatToEndOfStatement(); 5002 return Error(Loc, "too many conditions on IT instruction"); 5003 } 5004 unsigned Mask = 8; 5005 for (unsigned i = ITMask.size(); i != 0; --i) { 5006 char pos = ITMask[i - 1]; 5007 if (pos != 't' && pos != 'e') { 5008 Parser.EatToEndOfStatement(); 5009 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'"); 5010 } 5011 Mask >>= 1; 5012 if (ITMask[i - 1] == 't') 5013 Mask |= 8; 5014 } 5015 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc)); 5016 } 5017 5018 // FIXME: This is all a pretty gross hack. We should automatically handle 5019 // optional operands like this via tblgen. 5020 5021 // Next, add the CCOut and ConditionCode operands, if needed. 5022 // 5023 // For mnemonics which can ever incorporate a carry setting bit or predication 5024 // code, our matching model involves us always generating CCOut and 5025 // ConditionCode operands to match the mnemonic "as written" and then we let 5026 // the matcher deal with finding the right instruction or generating an 5027 // appropriate error. 5028 bool CanAcceptCarrySet, CanAcceptPredicationCode; 5029 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode); 5030 5031 // If we had a carry-set on an instruction that can't do that, issue an 5032 // error. 5033 if (!CanAcceptCarrySet && CarrySetting) { 5034 Parser.EatToEndOfStatement(); 5035 return Error(NameLoc, "instruction '" + Mnemonic + 5036 "' can not set flags, but 's' suffix specified"); 5037 } 5038 // If we had a predication code on an instruction that can't do that, issue an 5039 // error. 5040 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) { 5041 Parser.EatToEndOfStatement(); 5042 return Error(NameLoc, "instruction '" + Mnemonic + 5043 "' is not predicable, but condition code specified"); 5044 } 5045 5046 // Add the carry setting operand, if necessary. 5047 if (CanAcceptCarrySet) { 5048 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size()); 5049 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, 5050 Loc)); 5051 } 5052 5053 // Add the predication code operand, if necessary. 5054 if (CanAcceptPredicationCode) { 5055 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() + 5056 CarrySetting); 5057 Operands.push_back(ARMOperand::CreateCondCode( 5058 ARMCC::CondCodes(PredicationCode), Loc)); 5059 } 5060 5061 // Add the processor imod operand, if necessary. 5062 if (ProcessorIMod) { 5063 Operands.push_back(ARMOperand::CreateImm( 5064 MCConstantExpr::Create(ProcessorIMod, getContext()), 5065 NameLoc, NameLoc)); 5066 } 5067 5068 // Add the remaining tokens in the mnemonic. 5069 while (Next != StringRef::npos) { 5070 Start = Next; 5071 Next = Name.find('.', Start + 1); 5072 StringRef ExtraToken = Name.slice(Start, Next); 5073 5074 // Some NEON instructions have an optional datatype suffix that is 5075 // completely ignored. Check for that. 5076 if (isDataTypeToken(ExtraToken) && 5077 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken)) 5078 continue; 5079 5080 if (ExtraToken != ".n") { 5081 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 5082 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc)); 5083 } 5084 } 5085 5086 // Read the remaining operands. 5087 if (getLexer().isNot(AsmToken::EndOfStatement)) { 5088 // Read the first operand. 5089 if (parseOperand(Operands, Mnemonic)) { 5090 Parser.EatToEndOfStatement(); 5091 return true; 5092 } 5093 5094 while (getLexer().is(AsmToken::Comma)) { 5095 Parser.Lex(); // Eat the comma. 5096 5097 // Parse and remember the operand. 5098 if (parseOperand(Operands, Mnemonic)) { 5099 Parser.EatToEndOfStatement(); 5100 return true; 5101 } 5102 } 5103 } 5104 5105 if (getLexer().isNot(AsmToken::EndOfStatement)) { 5106 SMLoc Loc = getLexer().getLoc(); 5107 Parser.EatToEndOfStatement(); 5108 return Error(Loc, "unexpected token in argument list"); 5109 } 5110 5111 Parser.Lex(); // Consume the EndOfStatement 5112 5113 // Some instructions, mostly Thumb, have forms for the same mnemonic that 5114 // do and don't have a cc_out optional-def operand. With some spot-checks 5115 // of the operand list, we can figure out which variant we're trying to 5116 // parse and adjust accordingly before actually matching. We shouldn't ever 5117 // try to remove a cc_out operand that was explicitly set on the the 5118 // mnemonic, of course (CarrySetting == true). Reason number #317 the 5119 // table driven matcher doesn't fit well with the ARM instruction set. 5120 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) { 5121 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 5122 Operands.erase(Operands.begin() + 1); 5123 delete Op; 5124 } 5125 5126 // ARM mode 'blx' need special handling, as the register operand version 5127 // is predicable, but the label operand version is not. So, we can't rely 5128 // on the Mnemonic based checking to correctly figure out when to put 5129 // a k_CondCode operand in the list. If we're trying to match the label 5130 // version, remove the k_CondCode operand here. 5131 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && 5132 static_cast<ARMOperand*>(Operands[2])->isImm()) { 5133 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 5134 Operands.erase(Operands.begin() + 1); 5135 delete Op; 5136 } 5137 5138 // The vector-compare-to-zero instructions have a literal token "#0" at 5139 // the end that comes to here as an immediate operand. Convert it to a 5140 // token to play nicely with the matcher. 5141 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" || 5142 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 && 5143 static_cast<ARMOperand*>(Operands[5])->isImm()) { 5144 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]); 5145 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 5146 if (CE && CE->getValue() == 0) { 5147 Operands.erase(Operands.begin() + 5); 5148 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 5149 delete Op; 5150 } 5151 } 5152 // VCMP{E} does the same thing, but with a different operand count. 5153 if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 && 5154 static_cast<ARMOperand*>(Operands[4])->isImm()) { 5155 ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]); 5156 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 5157 if (CE && CE->getValue() == 0) { 5158 Operands.erase(Operands.begin() + 4); 5159 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 5160 delete Op; 5161 } 5162 } 5163 // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the 5164 // end. Convert it to a token here. Take care not to convert those 5165 // that should hit the Thumb2 encoding. 5166 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 && 5167 static_cast<ARMOperand*>(Operands[3])->isReg() && 5168 static_cast<ARMOperand*>(Operands[4])->isReg() && 5169 static_cast<ARMOperand*>(Operands[5])->isImm()) { 5170 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]); 5171 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 5172 if (CE && CE->getValue() == 0 && 5173 (isThumbOne() || 5174 // The cc_out operand matches the IT block. 5175 ((inITBlock() != CarrySetting) && 5176 // Neither register operand is a high register. 5177 (isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) && 5178 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()))))){ 5179 Operands.erase(Operands.begin() + 5); 5180 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 5181 delete Op; 5182 } 5183 } 5184 5185 return false; 5186 } 5187 5188 // Validate context-sensitive operand constraints. 5189 5190 // return 'true' if register list contains non-low GPR registers, 5191 // 'false' otherwise. If Reg is in the register list or is HiReg, set 5192 // 'containsReg' to true. 5193 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, 5194 unsigned HiReg, bool &containsReg) { 5195 containsReg = false; 5196 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 5197 unsigned OpReg = Inst.getOperand(i).getReg(); 5198 if (OpReg == Reg) 5199 containsReg = true; 5200 // Anything other than a low register isn't legal here. 5201 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) 5202 return true; 5203 } 5204 return false; 5205 } 5206 5207 // Check if the specified regisgter is in the register list of the inst, 5208 // starting at the indicated operand number. 5209 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) { 5210 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 5211 unsigned OpReg = Inst.getOperand(i).getReg(); 5212 if (OpReg == Reg) 5213 return true; 5214 } 5215 return false; 5216 } 5217 5218 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around 5219 // the ARMInsts array) instead. Getting that here requires awkward 5220 // API changes, though. Better way? 5221 namespace llvm { 5222 extern const MCInstrDesc ARMInsts[]; 5223 } 5224 static const MCInstrDesc &getInstDesc(unsigned Opcode) { 5225 return ARMInsts[Opcode]; 5226 } 5227 5228 // FIXME: We would really like to be able to tablegen'erate this. 5229 bool ARMAsmParser:: 5230 validateInstruction(MCInst &Inst, 5231 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 5232 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode()); 5233 SMLoc Loc = Operands[0]->getStartLoc(); 5234 // Check the IT block state first. 5235 // NOTE: BKPT instruction has the interesting property of being 5236 // allowed in IT blocks, but not being predicable. It just always 5237 // executes. 5238 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT && 5239 Inst.getOpcode() != ARM::BKPT) { 5240 unsigned bit = 1; 5241 if (ITState.FirstCond) 5242 ITState.FirstCond = false; 5243 else 5244 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1; 5245 // The instruction must be predicable. 5246 if (!MCID.isPredicable()) 5247 return Error(Loc, "instructions in IT block must be predicable"); 5248 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm(); 5249 unsigned ITCond = bit ? ITState.Cond : 5250 ARMCC::getOppositeCondition(ITState.Cond); 5251 if (Cond != ITCond) { 5252 // Find the condition code Operand to get its SMLoc information. 5253 SMLoc CondLoc; 5254 for (unsigned i = 1; i < Operands.size(); ++i) 5255 if (static_cast<ARMOperand*>(Operands[i])->isCondCode()) 5256 CondLoc = Operands[i]->getStartLoc(); 5257 return Error(CondLoc, "incorrect condition in IT block; got '" + 5258 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) + 5259 "', but expected '" + 5260 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'"); 5261 } 5262 // Check for non-'al' condition codes outside of the IT block. 5263 } else if (isThumbTwo() && MCID.isPredicable() && 5264 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != 5265 ARMCC::AL && Inst.getOpcode() != ARM::tB && 5266 Inst.getOpcode() != ARM::t2B) 5267 return Error(Loc, "predicated instructions must be in IT block"); 5268 5269 switch (Inst.getOpcode()) { 5270 case ARM::LDRD: 5271 case ARM::LDRD_PRE: 5272 case ARM::LDRD_POST: 5273 case ARM::LDREXD: { 5274 // Rt2 must be Rt + 1. 5275 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 5276 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5277 if (Rt2 != Rt + 1) 5278 return Error(Operands[3]->getStartLoc(), 5279 "destination operands must be sequential"); 5280 return false; 5281 } 5282 case ARM::STRD: { 5283 // Rt2 must be Rt + 1. 5284 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 5285 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5286 if (Rt2 != Rt + 1) 5287 return Error(Operands[3]->getStartLoc(), 5288 "source operands must be sequential"); 5289 return false; 5290 } 5291 case ARM::STRD_PRE: 5292 case ARM::STRD_POST: 5293 case ARM::STREXD: { 5294 // Rt2 must be Rt + 1. 5295 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5296 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg()); 5297 if (Rt2 != Rt + 1) 5298 return Error(Operands[3]->getStartLoc(), 5299 "source operands must be sequential"); 5300 return false; 5301 } 5302 case ARM::SBFX: 5303 case ARM::UBFX: { 5304 // width must be in range [1, 32-lsb] 5305 unsigned lsb = Inst.getOperand(2).getImm(); 5306 unsigned widthm1 = Inst.getOperand(3).getImm(); 5307 if (widthm1 >= 32 - lsb) 5308 return Error(Operands[5]->getStartLoc(), 5309 "bitfield width must be in range [1,32-lsb]"); 5310 return false; 5311 } 5312 case ARM::tLDMIA: { 5313 // If we're parsing Thumb2, the .w variant is available and handles 5314 // most cases that are normally illegal for a Thumb1 LDM 5315 // instruction. We'll make the transformation in processInstruction() 5316 // if necessary. 5317 // 5318 // Thumb LDM instructions are writeback iff the base register is not 5319 // in the register list. 5320 unsigned Rn = Inst.getOperand(0).getReg(); 5321 bool hasWritebackToken = 5322 (static_cast<ARMOperand*>(Operands[3])->isToken() && 5323 static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 5324 bool listContainsBase; 5325 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo()) 5326 return Error(Operands[3 + hasWritebackToken]->getStartLoc(), 5327 "registers must be in range r0-r7"); 5328 // If we should have writeback, then there should be a '!' token. 5329 if (!listContainsBase && !hasWritebackToken && !isThumbTwo()) 5330 return Error(Operands[2]->getStartLoc(), 5331 "writeback operator '!' expected"); 5332 // If we should not have writeback, there must not be a '!'. This is 5333 // true even for the 32-bit wide encodings. 5334 if (listContainsBase && hasWritebackToken) 5335 return Error(Operands[3]->getStartLoc(), 5336 "writeback operator '!' not allowed when base register " 5337 "in register list"); 5338 5339 break; 5340 } 5341 case ARM::t2LDMIA_UPD: { 5342 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) 5343 return Error(Operands[4]->getStartLoc(), 5344 "writeback operator '!' not allowed when base register " 5345 "in register list"); 5346 break; 5347 } 5348 case ARM::tMUL: { 5349 // The second source operand must be the same register as the destination 5350 // operand. 5351 // 5352 // In this case, we must directly check the parsed operands because the 5353 // cvtThumbMultiply() function is written in such a way that it guarantees 5354 // this first statement is always true for the new Inst. Essentially, the 5355 // destination is unconditionally copied into the second source operand 5356 // without checking to see if it matches what we actually parsed. 5357 if (Operands.size() == 6 && 5358 (((ARMOperand*)Operands[3])->getReg() != 5359 ((ARMOperand*)Operands[5])->getReg()) && 5360 (((ARMOperand*)Operands[3])->getReg() != 5361 ((ARMOperand*)Operands[4])->getReg())) { 5362 return Error(Operands[3]->getStartLoc(), 5363 "destination register must match source register"); 5364 } 5365 break; 5366 } 5367 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2, 5368 // so only issue a diagnostic for thumb1. The instructions will be 5369 // switched to the t2 encodings in processInstruction() if necessary. 5370 case ARM::tPOP: { 5371 bool listContainsBase; 5372 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) && 5373 !isThumbTwo()) 5374 return Error(Operands[2]->getStartLoc(), 5375 "registers must be in range r0-r7 or pc"); 5376 break; 5377 } 5378 case ARM::tPUSH: { 5379 bool listContainsBase; 5380 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) && 5381 !isThumbTwo()) 5382 return Error(Operands[2]->getStartLoc(), 5383 "registers must be in range r0-r7 or lr"); 5384 break; 5385 } 5386 case ARM::tSTMIA_UPD: { 5387 bool listContainsBase; 5388 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo()) 5389 return Error(Operands[4]->getStartLoc(), 5390 "registers must be in range r0-r7"); 5391 break; 5392 } 5393 case ARM::tADDrSP: { 5394 // If the non-SP source operand and the destination operand are not the 5395 // same, we need thumb2 (for the wide encoding), or we have an error. 5396 if (!isThumbTwo() && 5397 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 5398 return Error(Operands[4]->getStartLoc(), 5399 "source register must be the same as destination"); 5400 } 5401 break; 5402 } 5403 } 5404 5405 return false; 5406 } 5407 5408 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) { 5409 switch(Opc) { 5410 default: llvm_unreachable("unexpected opcode!"); 5411 // VST1LN 5412 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; 5413 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; 5414 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; 5415 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; 5416 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; 5417 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; 5418 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8; 5419 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16; 5420 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32; 5421 5422 // VST2LN 5423 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; 5424 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; 5425 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; 5426 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; 5427 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; 5428 5429 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; 5430 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; 5431 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; 5432 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; 5433 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; 5434 5435 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8; 5436 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16; 5437 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32; 5438 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16; 5439 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32; 5440 5441 // VST3LN 5442 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; 5443 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; 5444 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; 5445 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD; 5446 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; 5447 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; 5448 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; 5449 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; 5450 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD; 5451 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; 5452 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8; 5453 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16; 5454 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32; 5455 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16; 5456 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32; 5457 5458 // VST3 5459 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; 5460 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; 5461 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; 5462 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; 5463 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; 5464 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; 5465 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; 5466 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; 5467 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; 5468 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; 5469 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; 5470 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; 5471 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8; 5472 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16; 5473 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32; 5474 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8; 5475 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16; 5476 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32; 5477 5478 // VST4LN 5479 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; 5480 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; 5481 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; 5482 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD; 5483 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; 5484 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; 5485 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; 5486 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; 5487 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD; 5488 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; 5489 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8; 5490 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16; 5491 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32; 5492 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16; 5493 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32; 5494 5495 // VST4 5496 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; 5497 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; 5498 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; 5499 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; 5500 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; 5501 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; 5502 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; 5503 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; 5504 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; 5505 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; 5506 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; 5507 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; 5508 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8; 5509 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16; 5510 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32; 5511 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8; 5512 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16; 5513 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32; 5514 } 5515 } 5516 5517 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) { 5518 switch(Opc) { 5519 default: llvm_unreachable("unexpected opcode!"); 5520 // VLD1LN 5521 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; 5522 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; 5523 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; 5524 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; 5525 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; 5526 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; 5527 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8; 5528 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16; 5529 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32; 5530 5531 // VLD2LN 5532 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; 5533 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; 5534 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; 5535 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD; 5536 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; 5537 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; 5538 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; 5539 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; 5540 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD; 5541 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; 5542 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8; 5543 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16; 5544 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32; 5545 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16; 5546 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32; 5547 5548 // VLD3DUP 5549 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; 5550 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; 5551 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; 5552 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD; 5553 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD; 5554 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; 5555 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; 5556 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; 5557 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; 5558 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD; 5559 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; 5560 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; 5561 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8; 5562 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16; 5563 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32; 5564 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8; 5565 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16; 5566 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32; 5567 5568 // VLD3LN 5569 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; 5570 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; 5571 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; 5572 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD; 5573 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; 5574 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; 5575 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; 5576 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; 5577 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD; 5578 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; 5579 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8; 5580 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16; 5581 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32; 5582 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16; 5583 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32; 5584 5585 // VLD3 5586 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; 5587 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; 5588 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; 5589 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; 5590 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; 5591 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; 5592 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; 5593 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; 5594 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; 5595 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; 5596 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; 5597 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; 5598 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8; 5599 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16; 5600 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32; 5601 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8; 5602 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16; 5603 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32; 5604 5605 // VLD4LN 5606 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; 5607 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; 5608 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; 5609 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD; 5610 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; 5611 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; 5612 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; 5613 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; 5614 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; 5615 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; 5616 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8; 5617 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16; 5618 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32; 5619 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16; 5620 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32; 5621 5622 // VLD4DUP 5623 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; 5624 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; 5625 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; 5626 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD; 5627 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD; 5628 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; 5629 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; 5630 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; 5631 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; 5632 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD; 5633 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD; 5634 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; 5635 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8; 5636 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16; 5637 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32; 5638 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8; 5639 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16; 5640 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32; 5641 5642 // VLD4 5643 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; 5644 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; 5645 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; 5646 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; 5647 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; 5648 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; 5649 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; 5650 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; 5651 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; 5652 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; 5653 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; 5654 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; 5655 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8; 5656 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16; 5657 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32; 5658 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8; 5659 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16; 5660 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32; 5661 } 5662 } 5663 5664 bool ARMAsmParser:: 5665 processInstruction(MCInst &Inst, 5666 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 5667 switch (Inst.getOpcode()) { 5668 // Aliases for alternate PC+imm syntax of LDR instructions. 5669 case ARM::t2LDRpcrel: 5670 Inst.setOpcode(ARM::t2LDRpci); 5671 return true; 5672 case ARM::t2LDRBpcrel: 5673 Inst.setOpcode(ARM::t2LDRBpci); 5674 return true; 5675 case ARM::t2LDRHpcrel: 5676 Inst.setOpcode(ARM::t2LDRHpci); 5677 return true; 5678 case ARM::t2LDRSBpcrel: 5679 Inst.setOpcode(ARM::t2LDRSBpci); 5680 return true; 5681 case ARM::t2LDRSHpcrel: 5682 Inst.setOpcode(ARM::t2LDRSHpci); 5683 return true; 5684 // Handle NEON VST complex aliases. 5685 case ARM::VST1LNdWB_register_Asm_8: 5686 case ARM::VST1LNdWB_register_Asm_16: 5687 case ARM::VST1LNdWB_register_Asm_32: { 5688 MCInst TmpInst; 5689 // Shuffle the operands around so the lane index operand is in the 5690 // right place. 5691 unsigned Spacing; 5692 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5693 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5694 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5695 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5696 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5697 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5698 TmpInst.addOperand(Inst.getOperand(1)); // lane 5699 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5700 TmpInst.addOperand(Inst.getOperand(6)); 5701 Inst = TmpInst; 5702 return true; 5703 } 5704 5705 case ARM::VST2LNdWB_register_Asm_8: 5706 case ARM::VST2LNdWB_register_Asm_16: 5707 case ARM::VST2LNdWB_register_Asm_32: 5708 case ARM::VST2LNqWB_register_Asm_16: 5709 case ARM::VST2LNqWB_register_Asm_32: { 5710 MCInst TmpInst; 5711 // Shuffle the operands around so the lane index operand is in the 5712 // right place. 5713 unsigned Spacing; 5714 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5715 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5716 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5717 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5718 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5719 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5720 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5721 Spacing)); 5722 TmpInst.addOperand(Inst.getOperand(1)); // lane 5723 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5724 TmpInst.addOperand(Inst.getOperand(6)); 5725 Inst = TmpInst; 5726 return true; 5727 } 5728 5729 case ARM::VST3LNdWB_register_Asm_8: 5730 case ARM::VST3LNdWB_register_Asm_16: 5731 case ARM::VST3LNdWB_register_Asm_32: 5732 case ARM::VST3LNqWB_register_Asm_16: 5733 case ARM::VST3LNqWB_register_Asm_32: { 5734 MCInst TmpInst; 5735 // Shuffle the operands around so the lane index operand is in the 5736 // right place. 5737 unsigned Spacing; 5738 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5739 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5740 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5741 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5742 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5743 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5744 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5745 Spacing)); 5746 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5747 Spacing * 2)); 5748 TmpInst.addOperand(Inst.getOperand(1)); // lane 5749 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5750 TmpInst.addOperand(Inst.getOperand(6)); 5751 Inst = TmpInst; 5752 return true; 5753 } 5754 5755 case ARM::VST4LNdWB_register_Asm_8: 5756 case ARM::VST4LNdWB_register_Asm_16: 5757 case ARM::VST4LNdWB_register_Asm_32: 5758 case ARM::VST4LNqWB_register_Asm_16: 5759 case ARM::VST4LNqWB_register_Asm_32: { 5760 MCInst TmpInst; 5761 // Shuffle the operands around so the lane index operand is in the 5762 // right place. 5763 unsigned Spacing; 5764 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5765 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5766 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5767 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5768 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5769 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5770 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5771 Spacing)); 5772 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5773 Spacing * 2)); 5774 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5775 Spacing * 3)); 5776 TmpInst.addOperand(Inst.getOperand(1)); // lane 5777 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5778 TmpInst.addOperand(Inst.getOperand(6)); 5779 Inst = TmpInst; 5780 return true; 5781 } 5782 5783 case ARM::VST1LNdWB_fixed_Asm_8: 5784 case ARM::VST1LNdWB_fixed_Asm_16: 5785 case ARM::VST1LNdWB_fixed_Asm_32: { 5786 MCInst TmpInst; 5787 // Shuffle the operands around so the lane index operand is in the 5788 // right place. 5789 unsigned Spacing; 5790 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5791 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5792 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5793 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5794 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 5795 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5796 TmpInst.addOperand(Inst.getOperand(1)); // lane 5797 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5798 TmpInst.addOperand(Inst.getOperand(5)); 5799 Inst = TmpInst; 5800 return true; 5801 } 5802 5803 case ARM::VST2LNdWB_fixed_Asm_8: 5804 case ARM::VST2LNdWB_fixed_Asm_16: 5805 case ARM::VST2LNdWB_fixed_Asm_32: 5806 case ARM::VST2LNqWB_fixed_Asm_16: 5807 case ARM::VST2LNqWB_fixed_Asm_32: { 5808 MCInst TmpInst; 5809 // Shuffle the operands around so the lane index operand is in the 5810 // right place. 5811 unsigned Spacing; 5812 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5813 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5814 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5815 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5816 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 5817 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5818 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5819 Spacing)); 5820 TmpInst.addOperand(Inst.getOperand(1)); // lane 5821 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5822 TmpInst.addOperand(Inst.getOperand(5)); 5823 Inst = TmpInst; 5824 return true; 5825 } 5826 5827 case ARM::VST3LNdWB_fixed_Asm_8: 5828 case ARM::VST3LNdWB_fixed_Asm_16: 5829 case ARM::VST3LNdWB_fixed_Asm_32: 5830 case ARM::VST3LNqWB_fixed_Asm_16: 5831 case ARM::VST3LNqWB_fixed_Asm_32: { 5832 MCInst TmpInst; 5833 // Shuffle the operands around so the lane index operand is in the 5834 // right place. 5835 unsigned Spacing; 5836 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5837 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5838 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5839 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5840 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 5841 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5842 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5843 Spacing)); 5844 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5845 Spacing * 2)); 5846 TmpInst.addOperand(Inst.getOperand(1)); // lane 5847 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5848 TmpInst.addOperand(Inst.getOperand(5)); 5849 Inst = TmpInst; 5850 return true; 5851 } 5852 5853 case ARM::VST4LNdWB_fixed_Asm_8: 5854 case ARM::VST4LNdWB_fixed_Asm_16: 5855 case ARM::VST4LNdWB_fixed_Asm_32: 5856 case ARM::VST4LNqWB_fixed_Asm_16: 5857 case ARM::VST4LNqWB_fixed_Asm_32: { 5858 MCInst TmpInst; 5859 // Shuffle the operands around so the lane index operand is in the 5860 // right place. 5861 unsigned Spacing; 5862 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5863 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5864 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5865 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5866 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 5867 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5868 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5869 Spacing)); 5870 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5871 Spacing * 2)); 5872 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5873 Spacing * 3)); 5874 TmpInst.addOperand(Inst.getOperand(1)); // lane 5875 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5876 TmpInst.addOperand(Inst.getOperand(5)); 5877 Inst = TmpInst; 5878 return true; 5879 } 5880 5881 case ARM::VST1LNdAsm_8: 5882 case ARM::VST1LNdAsm_16: 5883 case ARM::VST1LNdAsm_32: { 5884 MCInst TmpInst; 5885 // Shuffle the operands around so the lane index operand is in the 5886 // right place. 5887 unsigned Spacing; 5888 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5889 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5890 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5891 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5892 TmpInst.addOperand(Inst.getOperand(1)); // lane 5893 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5894 TmpInst.addOperand(Inst.getOperand(5)); 5895 Inst = TmpInst; 5896 return true; 5897 } 5898 5899 case ARM::VST2LNdAsm_8: 5900 case ARM::VST2LNdAsm_16: 5901 case ARM::VST2LNdAsm_32: 5902 case ARM::VST2LNqAsm_16: 5903 case ARM::VST2LNqAsm_32: { 5904 MCInst TmpInst; 5905 // Shuffle the operands around so the lane index operand is in the 5906 // right place. 5907 unsigned Spacing; 5908 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5909 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5910 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5911 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5912 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5913 Spacing)); 5914 TmpInst.addOperand(Inst.getOperand(1)); // lane 5915 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5916 TmpInst.addOperand(Inst.getOperand(5)); 5917 Inst = TmpInst; 5918 return true; 5919 } 5920 5921 case ARM::VST3LNdAsm_8: 5922 case ARM::VST3LNdAsm_16: 5923 case ARM::VST3LNdAsm_32: 5924 case ARM::VST3LNqAsm_16: 5925 case ARM::VST3LNqAsm_32: { 5926 MCInst TmpInst; 5927 // Shuffle the operands around so the lane index operand is in the 5928 // right place. 5929 unsigned Spacing; 5930 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5931 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5932 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5933 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5934 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5935 Spacing)); 5936 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5937 Spacing * 2)); 5938 TmpInst.addOperand(Inst.getOperand(1)); // lane 5939 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5940 TmpInst.addOperand(Inst.getOperand(5)); 5941 Inst = TmpInst; 5942 return true; 5943 } 5944 5945 case ARM::VST4LNdAsm_8: 5946 case ARM::VST4LNdAsm_16: 5947 case ARM::VST4LNdAsm_32: 5948 case ARM::VST4LNqAsm_16: 5949 case ARM::VST4LNqAsm_32: { 5950 MCInst TmpInst; 5951 // Shuffle the operands around so the lane index operand is in the 5952 // right place. 5953 unsigned Spacing; 5954 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5955 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5956 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5957 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5958 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5959 Spacing)); 5960 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5961 Spacing * 2)); 5962 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5963 Spacing * 3)); 5964 TmpInst.addOperand(Inst.getOperand(1)); // lane 5965 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5966 TmpInst.addOperand(Inst.getOperand(5)); 5967 Inst = TmpInst; 5968 return true; 5969 } 5970 5971 // Handle NEON VLD complex aliases. 5972 case ARM::VLD1LNdWB_register_Asm_8: 5973 case ARM::VLD1LNdWB_register_Asm_16: 5974 case ARM::VLD1LNdWB_register_Asm_32: { 5975 MCInst TmpInst; 5976 // Shuffle the operands around so the lane index operand is in the 5977 // right place. 5978 unsigned Spacing; 5979 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 5980 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5981 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5982 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5983 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5984 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5985 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 5986 TmpInst.addOperand(Inst.getOperand(1)); // lane 5987 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5988 TmpInst.addOperand(Inst.getOperand(6)); 5989 Inst = TmpInst; 5990 return true; 5991 } 5992 5993 case ARM::VLD2LNdWB_register_Asm_8: 5994 case ARM::VLD2LNdWB_register_Asm_16: 5995 case ARM::VLD2LNdWB_register_Asm_32: 5996 case ARM::VLD2LNqWB_register_Asm_16: 5997 case ARM::VLD2LNqWB_register_Asm_32: { 5998 MCInst TmpInst; 5999 // Shuffle the operands around so the lane index operand is in the 6000 // right place. 6001 unsigned Spacing; 6002 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6003 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6004 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6005 Spacing)); 6006 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6007 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6008 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6009 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6010 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6011 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6012 Spacing)); 6013 TmpInst.addOperand(Inst.getOperand(1)); // lane 6014 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6015 TmpInst.addOperand(Inst.getOperand(6)); 6016 Inst = TmpInst; 6017 return true; 6018 } 6019 6020 case ARM::VLD3LNdWB_register_Asm_8: 6021 case ARM::VLD3LNdWB_register_Asm_16: 6022 case ARM::VLD3LNdWB_register_Asm_32: 6023 case ARM::VLD3LNqWB_register_Asm_16: 6024 case ARM::VLD3LNqWB_register_Asm_32: { 6025 MCInst TmpInst; 6026 // Shuffle the operands around so the lane index operand is in the 6027 // right place. 6028 unsigned Spacing; 6029 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6030 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6031 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6032 Spacing)); 6033 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6034 Spacing * 2)); 6035 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6036 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6037 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6038 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6039 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6040 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6041 Spacing)); 6042 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6043 Spacing * 2)); 6044 TmpInst.addOperand(Inst.getOperand(1)); // lane 6045 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6046 TmpInst.addOperand(Inst.getOperand(6)); 6047 Inst = TmpInst; 6048 return true; 6049 } 6050 6051 case ARM::VLD4LNdWB_register_Asm_8: 6052 case ARM::VLD4LNdWB_register_Asm_16: 6053 case ARM::VLD4LNdWB_register_Asm_32: 6054 case ARM::VLD4LNqWB_register_Asm_16: 6055 case ARM::VLD4LNqWB_register_Asm_32: { 6056 MCInst TmpInst; 6057 // Shuffle the operands around so the lane index operand is in the 6058 // right place. 6059 unsigned Spacing; 6060 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6061 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6062 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6063 Spacing)); 6064 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6065 Spacing * 2)); 6066 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6067 Spacing * 3)); 6068 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6069 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6070 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6071 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6072 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6073 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6074 Spacing)); 6075 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6076 Spacing * 2)); 6077 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6078 Spacing * 3)); 6079 TmpInst.addOperand(Inst.getOperand(1)); // lane 6080 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6081 TmpInst.addOperand(Inst.getOperand(6)); 6082 Inst = TmpInst; 6083 return true; 6084 } 6085 6086 case ARM::VLD1LNdWB_fixed_Asm_8: 6087 case ARM::VLD1LNdWB_fixed_Asm_16: 6088 case ARM::VLD1LNdWB_fixed_Asm_32: { 6089 MCInst TmpInst; 6090 // Shuffle the operands around so the lane index operand is in the 6091 // right place. 6092 unsigned Spacing; 6093 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6094 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6095 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6096 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6097 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6098 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6099 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6100 TmpInst.addOperand(Inst.getOperand(1)); // lane 6101 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6102 TmpInst.addOperand(Inst.getOperand(5)); 6103 Inst = TmpInst; 6104 return true; 6105 } 6106 6107 case ARM::VLD2LNdWB_fixed_Asm_8: 6108 case ARM::VLD2LNdWB_fixed_Asm_16: 6109 case ARM::VLD2LNdWB_fixed_Asm_32: 6110 case ARM::VLD2LNqWB_fixed_Asm_16: 6111 case ARM::VLD2LNqWB_fixed_Asm_32: { 6112 MCInst TmpInst; 6113 // Shuffle the operands around so the lane index operand is in the 6114 // right place. 6115 unsigned Spacing; 6116 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6117 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6118 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6119 Spacing)); 6120 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6121 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6122 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6123 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6124 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6125 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6126 Spacing)); 6127 TmpInst.addOperand(Inst.getOperand(1)); // lane 6128 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6129 TmpInst.addOperand(Inst.getOperand(5)); 6130 Inst = TmpInst; 6131 return true; 6132 } 6133 6134 case ARM::VLD3LNdWB_fixed_Asm_8: 6135 case ARM::VLD3LNdWB_fixed_Asm_16: 6136 case ARM::VLD3LNdWB_fixed_Asm_32: 6137 case ARM::VLD3LNqWB_fixed_Asm_16: 6138 case ARM::VLD3LNqWB_fixed_Asm_32: { 6139 MCInst TmpInst; 6140 // Shuffle the operands around so the lane index operand is in the 6141 // right place. 6142 unsigned Spacing; 6143 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6144 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6145 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6146 Spacing)); 6147 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6148 Spacing * 2)); 6149 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6150 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6151 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6152 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6153 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6154 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6155 Spacing)); 6156 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6157 Spacing * 2)); 6158 TmpInst.addOperand(Inst.getOperand(1)); // lane 6159 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6160 TmpInst.addOperand(Inst.getOperand(5)); 6161 Inst = TmpInst; 6162 return true; 6163 } 6164 6165 case ARM::VLD4LNdWB_fixed_Asm_8: 6166 case ARM::VLD4LNdWB_fixed_Asm_16: 6167 case ARM::VLD4LNdWB_fixed_Asm_32: 6168 case ARM::VLD4LNqWB_fixed_Asm_16: 6169 case ARM::VLD4LNqWB_fixed_Asm_32: { 6170 MCInst TmpInst; 6171 // Shuffle the operands around so the lane index operand is in the 6172 // right place. 6173 unsigned Spacing; 6174 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6175 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6176 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6177 Spacing)); 6178 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6179 Spacing * 2)); 6180 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6181 Spacing * 3)); 6182 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6183 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6184 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6185 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6186 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6187 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6188 Spacing)); 6189 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6190 Spacing * 2)); 6191 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6192 Spacing * 3)); 6193 TmpInst.addOperand(Inst.getOperand(1)); // lane 6194 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6195 TmpInst.addOperand(Inst.getOperand(5)); 6196 Inst = TmpInst; 6197 return true; 6198 } 6199 6200 case ARM::VLD1LNdAsm_8: 6201 case ARM::VLD1LNdAsm_16: 6202 case ARM::VLD1LNdAsm_32: { 6203 MCInst TmpInst; 6204 // Shuffle the operands around so the lane index operand is in the 6205 // right place. 6206 unsigned Spacing; 6207 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6208 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6209 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6210 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6211 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6212 TmpInst.addOperand(Inst.getOperand(1)); // lane 6213 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6214 TmpInst.addOperand(Inst.getOperand(5)); 6215 Inst = TmpInst; 6216 return true; 6217 } 6218 6219 case ARM::VLD2LNdAsm_8: 6220 case ARM::VLD2LNdAsm_16: 6221 case ARM::VLD2LNdAsm_32: 6222 case ARM::VLD2LNqAsm_16: 6223 case ARM::VLD2LNqAsm_32: { 6224 MCInst TmpInst; 6225 // Shuffle the operands around so the lane index operand is in the 6226 // right place. 6227 unsigned Spacing; 6228 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6229 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6230 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6231 Spacing)); 6232 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6233 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6234 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6235 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6236 Spacing)); 6237 TmpInst.addOperand(Inst.getOperand(1)); // lane 6238 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6239 TmpInst.addOperand(Inst.getOperand(5)); 6240 Inst = TmpInst; 6241 return true; 6242 } 6243 6244 case ARM::VLD3LNdAsm_8: 6245 case ARM::VLD3LNdAsm_16: 6246 case ARM::VLD3LNdAsm_32: 6247 case ARM::VLD3LNqAsm_16: 6248 case ARM::VLD3LNqAsm_32: { 6249 MCInst TmpInst; 6250 // Shuffle the operands around so the lane index operand is in the 6251 // right place. 6252 unsigned Spacing; 6253 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6254 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6255 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6256 Spacing)); 6257 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6258 Spacing * 2)); 6259 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6260 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6261 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6262 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6263 Spacing)); 6264 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6265 Spacing * 2)); 6266 TmpInst.addOperand(Inst.getOperand(1)); // lane 6267 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6268 TmpInst.addOperand(Inst.getOperand(5)); 6269 Inst = TmpInst; 6270 return true; 6271 } 6272 6273 case ARM::VLD4LNdAsm_8: 6274 case ARM::VLD4LNdAsm_16: 6275 case ARM::VLD4LNdAsm_32: 6276 case ARM::VLD4LNqAsm_16: 6277 case ARM::VLD4LNqAsm_32: { 6278 MCInst TmpInst; 6279 // Shuffle the operands around so the lane index operand is in the 6280 // right place. 6281 unsigned Spacing; 6282 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6283 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6284 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6285 Spacing)); 6286 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6287 Spacing * 2)); 6288 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6289 Spacing * 3)); 6290 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6291 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6292 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6293 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6294 Spacing)); 6295 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6296 Spacing * 2)); 6297 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6298 Spacing * 3)); 6299 TmpInst.addOperand(Inst.getOperand(1)); // lane 6300 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6301 TmpInst.addOperand(Inst.getOperand(5)); 6302 Inst = TmpInst; 6303 return true; 6304 } 6305 6306 // VLD3DUP single 3-element structure to all lanes instructions. 6307 case ARM::VLD3DUPdAsm_8: 6308 case ARM::VLD3DUPdAsm_16: 6309 case ARM::VLD3DUPdAsm_32: 6310 case ARM::VLD3DUPqAsm_8: 6311 case ARM::VLD3DUPqAsm_16: 6312 case ARM::VLD3DUPqAsm_32: { 6313 MCInst TmpInst; 6314 unsigned Spacing; 6315 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6316 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6317 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6318 Spacing)); 6319 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6320 Spacing * 2)); 6321 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6322 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6323 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6324 TmpInst.addOperand(Inst.getOperand(4)); 6325 Inst = TmpInst; 6326 return true; 6327 } 6328 6329 case ARM::VLD3DUPdWB_fixed_Asm_8: 6330 case ARM::VLD3DUPdWB_fixed_Asm_16: 6331 case ARM::VLD3DUPdWB_fixed_Asm_32: 6332 case ARM::VLD3DUPqWB_fixed_Asm_8: 6333 case ARM::VLD3DUPqWB_fixed_Asm_16: 6334 case ARM::VLD3DUPqWB_fixed_Asm_32: { 6335 MCInst TmpInst; 6336 unsigned Spacing; 6337 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6338 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6339 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6340 Spacing)); 6341 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6342 Spacing * 2)); 6343 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6344 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6345 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6346 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6347 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6348 TmpInst.addOperand(Inst.getOperand(4)); 6349 Inst = TmpInst; 6350 return true; 6351 } 6352 6353 case ARM::VLD3DUPdWB_register_Asm_8: 6354 case ARM::VLD3DUPdWB_register_Asm_16: 6355 case ARM::VLD3DUPdWB_register_Asm_32: 6356 case ARM::VLD3DUPqWB_register_Asm_8: 6357 case ARM::VLD3DUPqWB_register_Asm_16: 6358 case ARM::VLD3DUPqWB_register_Asm_32: { 6359 MCInst TmpInst; 6360 unsigned Spacing; 6361 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6362 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6363 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6364 Spacing)); 6365 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6366 Spacing * 2)); 6367 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6368 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6369 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6370 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6371 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6372 TmpInst.addOperand(Inst.getOperand(5)); 6373 Inst = TmpInst; 6374 return true; 6375 } 6376 6377 // VLD3 multiple 3-element structure instructions. 6378 case ARM::VLD3dAsm_8: 6379 case ARM::VLD3dAsm_16: 6380 case ARM::VLD3dAsm_32: 6381 case ARM::VLD3qAsm_8: 6382 case ARM::VLD3qAsm_16: 6383 case ARM::VLD3qAsm_32: { 6384 MCInst TmpInst; 6385 unsigned Spacing; 6386 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6387 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6388 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6389 Spacing)); 6390 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6391 Spacing * 2)); 6392 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6393 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6394 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6395 TmpInst.addOperand(Inst.getOperand(4)); 6396 Inst = TmpInst; 6397 return true; 6398 } 6399 6400 case ARM::VLD3dWB_fixed_Asm_8: 6401 case ARM::VLD3dWB_fixed_Asm_16: 6402 case ARM::VLD3dWB_fixed_Asm_32: 6403 case ARM::VLD3qWB_fixed_Asm_8: 6404 case ARM::VLD3qWB_fixed_Asm_16: 6405 case ARM::VLD3qWB_fixed_Asm_32: { 6406 MCInst TmpInst; 6407 unsigned Spacing; 6408 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6409 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6410 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6411 Spacing)); 6412 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6413 Spacing * 2)); 6414 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6415 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6416 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6417 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6418 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6419 TmpInst.addOperand(Inst.getOperand(4)); 6420 Inst = TmpInst; 6421 return true; 6422 } 6423 6424 case ARM::VLD3dWB_register_Asm_8: 6425 case ARM::VLD3dWB_register_Asm_16: 6426 case ARM::VLD3dWB_register_Asm_32: 6427 case ARM::VLD3qWB_register_Asm_8: 6428 case ARM::VLD3qWB_register_Asm_16: 6429 case ARM::VLD3qWB_register_Asm_32: { 6430 MCInst TmpInst; 6431 unsigned Spacing; 6432 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6433 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6434 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6435 Spacing)); 6436 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6437 Spacing * 2)); 6438 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6439 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6440 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6441 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6442 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6443 TmpInst.addOperand(Inst.getOperand(5)); 6444 Inst = TmpInst; 6445 return true; 6446 } 6447 6448 // VLD4DUP single 3-element structure to all lanes instructions. 6449 case ARM::VLD4DUPdAsm_8: 6450 case ARM::VLD4DUPdAsm_16: 6451 case ARM::VLD4DUPdAsm_32: 6452 case ARM::VLD4DUPqAsm_8: 6453 case ARM::VLD4DUPqAsm_16: 6454 case ARM::VLD4DUPqAsm_32: { 6455 MCInst TmpInst; 6456 unsigned Spacing; 6457 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6458 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6459 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6460 Spacing)); 6461 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6462 Spacing * 2)); 6463 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6464 Spacing * 3)); 6465 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6466 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6467 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6468 TmpInst.addOperand(Inst.getOperand(4)); 6469 Inst = TmpInst; 6470 return true; 6471 } 6472 6473 case ARM::VLD4DUPdWB_fixed_Asm_8: 6474 case ARM::VLD4DUPdWB_fixed_Asm_16: 6475 case ARM::VLD4DUPdWB_fixed_Asm_32: 6476 case ARM::VLD4DUPqWB_fixed_Asm_8: 6477 case ARM::VLD4DUPqWB_fixed_Asm_16: 6478 case ARM::VLD4DUPqWB_fixed_Asm_32: { 6479 MCInst TmpInst; 6480 unsigned Spacing; 6481 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6482 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6483 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6484 Spacing)); 6485 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6486 Spacing * 2)); 6487 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6488 Spacing * 3)); 6489 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6490 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6491 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6492 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6493 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6494 TmpInst.addOperand(Inst.getOperand(4)); 6495 Inst = TmpInst; 6496 return true; 6497 } 6498 6499 case ARM::VLD4DUPdWB_register_Asm_8: 6500 case ARM::VLD4DUPdWB_register_Asm_16: 6501 case ARM::VLD4DUPdWB_register_Asm_32: 6502 case ARM::VLD4DUPqWB_register_Asm_8: 6503 case ARM::VLD4DUPqWB_register_Asm_16: 6504 case ARM::VLD4DUPqWB_register_Asm_32: { 6505 MCInst TmpInst; 6506 unsigned Spacing; 6507 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6508 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6509 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6510 Spacing)); 6511 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6512 Spacing * 2)); 6513 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6514 Spacing * 3)); 6515 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6516 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6517 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6518 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6519 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6520 TmpInst.addOperand(Inst.getOperand(5)); 6521 Inst = TmpInst; 6522 return true; 6523 } 6524 6525 // VLD4 multiple 4-element structure instructions. 6526 case ARM::VLD4dAsm_8: 6527 case ARM::VLD4dAsm_16: 6528 case ARM::VLD4dAsm_32: 6529 case ARM::VLD4qAsm_8: 6530 case ARM::VLD4qAsm_16: 6531 case ARM::VLD4qAsm_32: { 6532 MCInst TmpInst; 6533 unsigned Spacing; 6534 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6535 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6536 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6537 Spacing)); 6538 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6539 Spacing * 2)); 6540 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6541 Spacing * 3)); 6542 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6543 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6544 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6545 TmpInst.addOperand(Inst.getOperand(4)); 6546 Inst = TmpInst; 6547 return true; 6548 } 6549 6550 case ARM::VLD4dWB_fixed_Asm_8: 6551 case ARM::VLD4dWB_fixed_Asm_16: 6552 case ARM::VLD4dWB_fixed_Asm_32: 6553 case ARM::VLD4qWB_fixed_Asm_8: 6554 case ARM::VLD4qWB_fixed_Asm_16: 6555 case ARM::VLD4qWB_fixed_Asm_32: { 6556 MCInst TmpInst; 6557 unsigned Spacing; 6558 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6559 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6560 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6561 Spacing)); 6562 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6563 Spacing * 2)); 6564 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6565 Spacing * 3)); 6566 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6567 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6568 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6569 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6570 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6571 TmpInst.addOperand(Inst.getOperand(4)); 6572 Inst = TmpInst; 6573 return true; 6574 } 6575 6576 case ARM::VLD4dWB_register_Asm_8: 6577 case ARM::VLD4dWB_register_Asm_16: 6578 case ARM::VLD4dWB_register_Asm_32: 6579 case ARM::VLD4qWB_register_Asm_8: 6580 case ARM::VLD4qWB_register_Asm_16: 6581 case ARM::VLD4qWB_register_Asm_32: { 6582 MCInst TmpInst; 6583 unsigned Spacing; 6584 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6585 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6586 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6587 Spacing)); 6588 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6589 Spacing * 2)); 6590 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6591 Spacing * 3)); 6592 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6593 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6594 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6595 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6596 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6597 TmpInst.addOperand(Inst.getOperand(5)); 6598 Inst = TmpInst; 6599 return true; 6600 } 6601 6602 // VST3 multiple 3-element structure instructions. 6603 case ARM::VST3dAsm_8: 6604 case ARM::VST3dAsm_16: 6605 case ARM::VST3dAsm_32: 6606 case ARM::VST3qAsm_8: 6607 case ARM::VST3qAsm_16: 6608 case ARM::VST3qAsm_32: { 6609 MCInst TmpInst; 6610 unsigned Spacing; 6611 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6612 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6613 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6614 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6615 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6616 Spacing)); 6617 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6618 Spacing * 2)); 6619 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6620 TmpInst.addOperand(Inst.getOperand(4)); 6621 Inst = TmpInst; 6622 return true; 6623 } 6624 6625 case ARM::VST3dWB_fixed_Asm_8: 6626 case ARM::VST3dWB_fixed_Asm_16: 6627 case ARM::VST3dWB_fixed_Asm_32: 6628 case ARM::VST3qWB_fixed_Asm_8: 6629 case ARM::VST3qWB_fixed_Asm_16: 6630 case ARM::VST3qWB_fixed_Asm_32: { 6631 MCInst TmpInst; 6632 unsigned Spacing; 6633 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6634 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6635 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6636 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6637 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6638 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6639 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6640 Spacing)); 6641 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6642 Spacing * 2)); 6643 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6644 TmpInst.addOperand(Inst.getOperand(4)); 6645 Inst = TmpInst; 6646 return true; 6647 } 6648 6649 case ARM::VST3dWB_register_Asm_8: 6650 case ARM::VST3dWB_register_Asm_16: 6651 case ARM::VST3dWB_register_Asm_32: 6652 case ARM::VST3qWB_register_Asm_8: 6653 case ARM::VST3qWB_register_Asm_16: 6654 case ARM::VST3qWB_register_Asm_32: { 6655 MCInst TmpInst; 6656 unsigned Spacing; 6657 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6658 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6659 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6660 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6661 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6662 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6663 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6664 Spacing)); 6665 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6666 Spacing * 2)); 6667 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6668 TmpInst.addOperand(Inst.getOperand(5)); 6669 Inst = TmpInst; 6670 return true; 6671 } 6672 6673 // VST4 multiple 3-element structure instructions. 6674 case ARM::VST4dAsm_8: 6675 case ARM::VST4dAsm_16: 6676 case ARM::VST4dAsm_32: 6677 case ARM::VST4qAsm_8: 6678 case ARM::VST4qAsm_16: 6679 case ARM::VST4qAsm_32: { 6680 MCInst TmpInst; 6681 unsigned Spacing; 6682 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6683 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6684 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6685 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6686 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6687 Spacing)); 6688 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6689 Spacing * 2)); 6690 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6691 Spacing * 3)); 6692 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6693 TmpInst.addOperand(Inst.getOperand(4)); 6694 Inst = TmpInst; 6695 return true; 6696 } 6697 6698 case ARM::VST4dWB_fixed_Asm_8: 6699 case ARM::VST4dWB_fixed_Asm_16: 6700 case ARM::VST4dWB_fixed_Asm_32: 6701 case ARM::VST4qWB_fixed_Asm_8: 6702 case ARM::VST4qWB_fixed_Asm_16: 6703 case ARM::VST4qWB_fixed_Asm_32: { 6704 MCInst TmpInst; 6705 unsigned Spacing; 6706 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6707 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6708 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6709 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6710 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6711 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6712 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6713 Spacing)); 6714 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6715 Spacing * 2)); 6716 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6717 Spacing * 3)); 6718 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6719 TmpInst.addOperand(Inst.getOperand(4)); 6720 Inst = TmpInst; 6721 return true; 6722 } 6723 6724 case ARM::VST4dWB_register_Asm_8: 6725 case ARM::VST4dWB_register_Asm_16: 6726 case ARM::VST4dWB_register_Asm_32: 6727 case ARM::VST4qWB_register_Asm_8: 6728 case ARM::VST4qWB_register_Asm_16: 6729 case ARM::VST4qWB_register_Asm_32: { 6730 MCInst TmpInst; 6731 unsigned Spacing; 6732 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6733 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6734 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6735 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6736 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6737 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6738 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6739 Spacing)); 6740 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6741 Spacing * 2)); 6742 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6743 Spacing * 3)); 6744 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6745 TmpInst.addOperand(Inst.getOperand(5)); 6746 Inst = TmpInst; 6747 return true; 6748 } 6749 6750 // Handle encoding choice for the shift-immediate instructions. 6751 case ARM::t2LSLri: 6752 case ARM::t2LSRri: 6753 case ARM::t2ASRri: { 6754 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 6755 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 6756 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && 6757 !(static_cast<ARMOperand*>(Operands[3])->isToken() && 6758 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) { 6759 unsigned NewOpc; 6760 switch (Inst.getOpcode()) { 6761 default: llvm_unreachable("unexpected opcode"); 6762 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break; 6763 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break; 6764 case ARM::t2ASRri: NewOpc = ARM::tASRri; break; 6765 } 6766 // The Thumb1 operands aren't in the same order. Awesome, eh? 6767 MCInst TmpInst; 6768 TmpInst.setOpcode(NewOpc); 6769 TmpInst.addOperand(Inst.getOperand(0)); 6770 TmpInst.addOperand(Inst.getOperand(5)); 6771 TmpInst.addOperand(Inst.getOperand(1)); 6772 TmpInst.addOperand(Inst.getOperand(2)); 6773 TmpInst.addOperand(Inst.getOperand(3)); 6774 TmpInst.addOperand(Inst.getOperand(4)); 6775 Inst = TmpInst; 6776 return true; 6777 } 6778 return false; 6779 } 6780 6781 // Handle the Thumb2 mode MOV complex aliases. 6782 case ARM::t2MOVsr: 6783 case ARM::t2MOVSsr: { 6784 // Which instruction to expand to depends on the CCOut operand and 6785 // whether we're in an IT block if the register operands are low 6786 // registers. 6787 bool isNarrow = false; 6788 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 6789 isARMLowRegister(Inst.getOperand(1).getReg()) && 6790 isARMLowRegister(Inst.getOperand(2).getReg()) && 6791 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 6792 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr)) 6793 isNarrow = true; 6794 MCInst TmpInst; 6795 unsigned newOpc; 6796 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) { 6797 default: llvm_unreachable("unexpected opcode!"); 6798 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break; 6799 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break; 6800 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break; 6801 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break; 6802 } 6803 TmpInst.setOpcode(newOpc); 6804 TmpInst.addOperand(Inst.getOperand(0)); // Rd 6805 if (isNarrow) 6806 TmpInst.addOperand(MCOperand::CreateReg( 6807 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 6808 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6809 TmpInst.addOperand(Inst.getOperand(2)); // Rm 6810 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6811 TmpInst.addOperand(Inst.getOperand(5)); 6812 if (!isNarrow) 6813 TmpInst.addOperand(MCOperand::CreateReg( 6814 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 6815 Inst = TmpInst; 6816 return true; 6817 } 6818 case ARM::t2MOVsi: 6819 case ARM::t2MOVSsi: { 6820 // Which instruction to expand to depends on the CCOut operand and 6821 // whether we're in an IT block if the register operands are low 6822 // registers. 6823 bool isNarrow = false; 6824 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 6825 isARMLowRegister(Inst.getOperand(1).getReg()) && 6826 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi)) 6827 isNarrow = true; 6828 MCInst TmpInst; 6829 unsigned newOpc; 6830 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) { 6831 default: llvm_unreachable("unexpected opcode!"); 6832 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break; 6833 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break; 6834 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break; 6835 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break; 6836 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break; 6837 } 6838 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()); 6839 if (Amount == 32) Amount = 0; 6840 TmpInst.setOpcode(newOpc); 6841 TmpInst.addOperand(Inst.getOperand(0)); // Rd 6842 if (isNarrow) 6843 TmpInst.addOperand(MCOperand::CreateReg( 6844 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 6845 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6846 if (newOpc != ARM::t2RRX) 6847 TmpInst.addOperand(MCOperand::CreateImm(Amount)); 6848 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6849 TmpInst.addOperand(Inst.getOperand(4)); 6850 if (!isNarrow) 6851 TmpInst.addOperand(MCOperand::CreateReg( 6852 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 6853 Inst = TmpInst; 6854 return true; 6855 } 6856 // Handle the ARM mode MOV complex aliases. 6857 case ARM::ASRr: 6858 case ARM::LSRr: 6859 case ARM::LSLr: 6860 case ARM::RORr: { 6861 ARM_AM::ShiftOpc ShiftTy; 6862 switch(Inst.getOpcode()) { 6863 default: llvm_unreachable("unexpected opcode!"); 6864 case ARM::ASRr: ShiftTy = ARM_AM::asr; break; 6865 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break; 6866 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break; 6867 case ARM::RORr: ShiftTy = ARM_AM::ror; break; 6868 } 6869 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0); 6870 MCInst TmpInst; 6871 TmpInst.setOpcode(ARM::MOVsr); 6872 TmpInst.addOperand(Inst.getOperand(0)); // Rd 6873 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6874 TmpInst.addOperand(Inst.getOperand(2)); // Rm 6875 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 6876 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6877 TmpInst.addOperand(Inst.getOperand(4)); 6878 TmpInst.addOperand(Inst.getOperand(5)); // cc_out 6879 Inst = TmpInst; 6880 return true; 6881 } 6882 case ARM::ASRi: 6883 case ARM::LSRi: 6884 case ARM::LSLi: 6885 case ARM::RORi: { 6886 ARM_AM::ShiftOpc ShiftTy; 6887 switch(Inst.getOpcode()) { 6888 default: llvm_unreachable("unexpected opcode!"); 6889 case ARM::ASRi: ShiftTy = ARM_AM::asr; break; 6890 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break; 6891 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break; 6892 case ARM::RORi: ShiftTy = ARM_AM::ror; break; 6893 } 6894 // A shift by zero is a plain MOVr, not a MOVsi. 6895 unsigned Amt = Inst.getOperand(2).getImm(); 6896 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi; 6897 // A shift by 32 should be encoded as 0 when permitted 6898 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr)) 6899 Amt = 0; 6900 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt); 6901 MCInst TmpInst; 6902 TmpInst.setOpcode(Opc); 6903 TmpInst.addOperand(Inst.getOperand(0)); // Rd 6904 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6905 if (Opc == ARM::MOVsi) 6906 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 6907 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6908 TmpInst.addOperand(Inst.getOperand(4)); 6909 TmpInst.addOperand(Inst.getOperand(5)); // cc_out 6910 Inst = TmpInst; 6911 return true; 6912 } 6913 case ARM::RRXi: { 6914 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0); 6915 MCInst TmpInst; 6916 TmpInst.setOpcode(ARM::MOVsi); 6917 TmpInst.addOperand(Inst.getOperand(0)); // Rd 6918 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6919 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 6920 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 6921 TmpInst.addOperand(Inst.getOperand(3)); 6922 TmpInst.addOperand(Inst.getOperand(4)); // cc_out 6923 Inst = TmpInst; 6924 return true; 6925 } 6926 case ARM::t2LDMIA_UPD: { 6927 // If this is a load of a single register, then we should use 6928 // a post-indexed LDR instruction instead, per the ARM ARM. 6929 if (Inst.getNumOperands() != 5) 6930 return false; 6931 MCInst TmpInst; 6932 TmpInst.setOpcode(ARM::t2LDR_POST); 6933 TmpInst.addOperand(Inst.getOperand(4)); // Rt 6934 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 6935 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6936 TmpInst.addOperand(MCOperand::CreateImm(4)); 6937 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 6938 TmpInst.addOperand(Inst.getOperand(3)); 6939 Inst = TmpInst; 6940 return true; 6941 } 6942 case ARM::t2STMDB_UPD: { 6943 // If this is a store of a single register, then we should use 6944 // a pre-indexed STR instruction instead, per the ARM ARM. 6945 if (Inst.getNumOperands() != 5) 6946 return false; 6947 MCInst TmpInst; 6948 TmpInst.setOpcode(ARM::t2STR_PRE); 6949 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 6950 TmpInst.addOperand(Inst.getOperand(4)); // Rt 6951 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6952 TmpInst.addOperand(MCOperand::CreateImm(-4)); 6953 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 6954 TmpInst.addOperand(Inst.getOperand(3)); 6955 Inst = TmpInst; 6956 return true; 6957 } 6958 case ARM::LDMIA_UPD: 6959 // If this is a load of a single register via a 'pop', then we should use 6960 // a post-indexed LDR instruction instead, per the ARM ARM. 6961 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" && 6962 Inst.getNumOperands() == 5) { 6963 MCInst TmpInst; 6964 TmpInst.setOpcode(ARM::LDR_POST_IMM); 6965 TmpInst.addOperand(Inst.getOperand(4)); // Rt 6966 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 6967 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6968 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset 6969 TmpInst.addOperand(MCOperand::CreateImm(4)); 6970 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 6971 TmpInst.addOperand(Inst.getOperand(3)); 6972 Inst = TmpInst; 6973 return true; 6974 } 6975 break; 6976 case ARM::STMDB_UPD: 6977 // If this is a store of a single register via a 'push', then we should use 6978 // a pre-indexed STR instruction instead, per the ARM ARM. 6979 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" && 6980 Inst.getNumOperands() == 5) { 6981 MCInst TmpInst; 6982 TmpInst.setOpcode(ARM::STR_PRE_IMM); 6983 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 6984 TmpInst.addOperand(Inst.getOperand(4)); // Rt 6985 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12 6986 TmpInst.addOperand(MCOperand::CreateImm(-4)); 6987 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 6988 TmpInst.addOperand(Inst.getOperand(3)); 6989 Inst = TmpInst; 6990 } 6991 break; 6992 case ARM::t2ADDri12: 6993 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add" 6994 // mnemonic was used (not "addw"), encoding T3 is preferred. 6995 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" || 6996 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 6997 break; 6998 Inst.setOpcode(ARM::t2ADDri); 6999 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 7000 break; 7001 case ARM::t2SUBri12: 7002 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub" 7003 // mnemonic was used (not "subw"), encoding T3 is preferred. 7004 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" || 7005 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 7006 break; 7007 Inst.setOpcode(ARM::t2SUBri); 7008 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 7009 break; 7010 case ARM::tADDi8: 7011 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 7012 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 7013 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 7014 // to encoding T1 if <Rd> is omitted." 7015 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 7016 Inst.setOpcode(ARM::tADDi3); 7017 return true; 7018 } 7019 break; 7020 case ARM::tSUBi8: 7021 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 7022 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 7023 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 7024 // to encoding T1 if <Rd> is omitted." 7025 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 7026 Inst.setOpcode(ARM::tSUBi3); 7027 return true; 7028 } 7029 break; 7030 case ARM::t2ADDri: 7031 case ARM::t2SUBri: { 7032 // If the destination and first source operand are the same, and 7033 // the flags are compatible with the current IT status, use encoding T2 7034 // instead of T3. For compatibility with the system 'as'. Make sure the 7035 // wide encoding wasn't explicit. 7036 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 7037 !isARMLowRegister(Inst.getOperand(0).getReg()) || 7038 (unsigned)Inst.getOperand(2).getImm() > 255 || 7039 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) || 7040 (inITBlock() && Inst.getOperand(5).getReg() != 0)) || 7041 (static_cast<ARMOperand*>(Operands[3])->isToken() && 7042 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) 7043 break; 7044 MCInst TmpInst; 7045 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ? 7046 ARM::tADDi8 : ARM::tSUBi8); 7047 TmpInst.addOperand(Inst.getOperand(0)); 7048 TmpInst.addOperand(Inst.getOperand(5)); 7049 TmpInst.addOperand(Inst.getOperand(0)); 7050 TmpInst.addOperand(Inst.getOperand(2)); 7051 TmpInst.addOperand(Inst.getOperand(3)); 7052 TmpInst.addOperand(Inst.getOperand(4)); 7053 Inst = TmpInst; 7054 return true; 7055 } 7056 case ARM::t2ADDrr: { 7057 // If the destination and first source operand are the same, and 7058 // there's no setting of the flags, use encoding T2 instead of T3. 7059 // Note that this is only for ADD, not SUB. This mirrors the system 7060 // 'as' behaviour. Make sure the wide encoding wasn't explicit. 7061 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 7062 Inst.getOperand(5).getReg() != 0 || 7063 (static_cast<ARMOperand*>(Operands[3])->isToken() && 7064 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) 7065 break; 7066 MCInst TmpInst; 7067 TmpInst.setOpcode(ARM::tADDhirr); 7068 TmpInst.addOperand(Inst.getOperand(0)); 7069 TmpInst.addOperand(Inst.getOperand(0)); 7070 TmpInst.addOperand(Inst.getOperand(2)); 7071 TmpInst.addOperand(Inst.getOperand(3)); 7072 TmpInst.addOperand(Inst.getOperand(4)); 7073 Inst = TmpInst; 7074 return true; 7075 } 7076 case ARM::tADDrSP: { 7077 // If the non-SP source operand and the destination operand are not the 7078 // same, we need to use the 32-bit encoding if it's available. 7079 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 7080 Inst.setOpcode(ARM::t2ADDrr); 7081 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 7082 return true; 7083 } 7084 break; 7085 } 7086 case ARM::tB: 7087 // A Thumb conditional branch outside of an IT block is a tBcc. 7088 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) { 7089 Inst.setOpcode(ARM::tBcc); 7090 return true; 7091 } 7092 break; 7093 case ARM::t2B: 7094 // A Thumb2 conditional branch outside of an IT block is a t2Bcc. 7095 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){ 7096 Inst.setOpcode(ARM::t2Bcc); 7097 return true; 7098 } 7099 break; 7100 case ARM::t2Bcc: 7101 // If the conditional is AL or we're in an IT block, we really want t2B. 7102 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) { 7103 Inst.setOpcode(ARM::t2B); 7104 return true; 7105 } 7106 break; 7107 case ARM::tBcc: 7108 // If the conditional is AL, we really want tB. 7109 if (Inst.getOperand(1).getImm() == ARMCC::AL) { 7110 Inst.setOpcode(ARM::tB); 7111 return true; 7112 } 7113 break; 7114 case ARM::tLDMIA: { 7115 // If the register list contains any high registers, or if the writeback 7116 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding 7117 // instead if we're in Thumb2. Otherwise, this should have generated 7118 // an error in validateInstruction(). 7119 unsigned Rn = Inst.getOperand(0).getReg(); 7120 bool hasWritebackToken = 7121 (static_cast<ARMOperand*>(Operands[3])->isToken() && 7122 static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 7123 bool listContainsBase; 7124 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) || 7125 (!listContainsBase && !hasWritebackToken) || 7126 (listContainsBase && hasWritebackToken)) { 7127 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 7128 assert (isThumbTwo()); 7129 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA); 7130 // If we're switching to the updating version, we need to insert 7131 // the writeback tied operand. 7132 if (hasWritebackToken) 7133 Inst.insert(Inst.begin(), 7134 MCOperand::CreateReg(Inst.getOperand(0).getReg())); 7135 return true; 7136 } 7137 break; 7138 } 7139 case ARM::tSTMIA_UPD: { 7140 // If the register list contains any high registers, we need to use 7141 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 7142 // should have generated an error in validateInstruction(). 7143 unsigned Rn = Inst.getOperand(0).getReg(); 7144 bool listContainsBase; 7145 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) { 7146 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 7147 assert (isThumbTwo()); 7148 Inst.setOpcode(ARM::t2STMIA_UPD); 7149 return true; 7150 } 7151 break; 7152 } 7153 case ARM::tPOP: { 7154 bool listContainsBase; 7155 // If the register list contains any high registers, we need to use 7156 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 7157 // should have generated an error in validateInstruction(). 7158 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase)) 7159 return false; 7160 assert (isThumbTwo()); 7161 Inst.setOpcode(ARM::t2LDMIA_UPD); 7162 // Add the base register and writeback operands. 7163 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7164 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7165 return true; 7166 } 7167 case ARM::tPUSH: { 7168 bool listContainsBase; 7169 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase)) 7170 return false; 7171 assert (isThumbTwo()); 7172 Inst.setOpcode(ARM::t2STMDB_UPD); 7173 // Add the base register and writeback operands. 7174 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7175 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7176 return true; 7177 } 7178 case ARM::t2MOVi: { 7179 // If we can use the 16-bit encoding and the user didn't explicitly 7180 // request the 32-bit variant, transform it here. 7181 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7182 (unsigned)Inst.getOperand(1).getImm() <= 255 && 7183 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL && 7184 Inst.getOperand(4).getReg() == ARM::CPSR) || 7185 (inITBlock() && Inst.getOperand(4).getReg() == 0)) && 7186 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 7187 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 7188 // The operands aren't in the same order for tMOVi8... 7189 MCInst TmpInst; 7190 TmpInst.setOpcode(ARM::tMOVi8); 7191 TmpInst.addOperand(Inst.getOperand(0)); 7192 TmpInst.addOperand(Inst.getOperand(4)); 7193 TmpInst.addOperand(Inst.getOperand(1)); 7194 TmpInst.addOperand(Inst.getOperand(2)); 7195 TmpInst.addOperand(Inst.getOperand(3)); 7196 Inst = TmpInst; 7197 return true; 7198 } 7199 break; 7200 } 7201 case ARM::t2MOVr: { 7202 // If we can use the 16-bit encoding and the user didn't explicitly 7203 // request the 32-bit variant, transform it here. 7204 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7205 isARMLowRegister(Inst.getOperand(1).getReg()) && 7206 Inst.getOperand(2).getImm() == ARMCC::AL && 7207 Inst.getOperand(4).getReg() == ARM::CPSR && 7208 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 7209 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 7210 // The operands aren't the same for tMOV[S]r... (no cc_out) 7211 MCInst TmpInst; 7212 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr); 7213 TmpInst.addOperand(Inst.getOperand(0)); 7214 TmpInst.addOperand(Inst.getOperand(1)); 7215 TmpInst.addOperand(Inst.getOperand(2)); 7216 TmpInst.addOperand(Inst.getOperand(3)); 7217 Inst = TmpInst; 7218 return true; 7219 } 7220 break; 7221 } 7222 case ARM::t2SXTH: 7223 case ARM::t2SXTB: 7224 case ARM::t2UXTH: 7225 case ARM::t2UXTB: { 7226 // If we can use the 16-bit encoding and the user didn't explicitly 7227 // request the 32-bit variant, transform it here. 7228 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7229 isARMLowRegister(Inst.getOperand(1).getReg()) && 7230 Inst.getOperand(2).getImm() == 0 && 7231 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 7232 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 7233 unsigned NewOpc; 7234 switch (Inst.getOpcode()) { 7235 default: llvm_unreachable("Illegal opcode!"); 7236 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; 7237 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; 7238 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; 7239 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break; 7240 } 7241 // The operands aren't the same for thumb1 (no rotate operand). 7242 MCInst TmpInst; 7243 TmpInst.setOpcode(NewOpc); 7244 TmpInst.addOperand(Inst.getOperand(0)); 7245 TmpInst.addOperand(Inst.getOperand(1)); 7246 TmpInst.addOperand(Inst.getOperand(3)); 7247 TmpInst.addOperand(Inst.getOperand(4)); 7248 Inst = TmpInst; 7249 return true; 7250 } 7251 break; 7252 } 7253 case ARM::MOVsi: { 7254 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm()); 7255 // rrx shifts and asr/lsr of #32 is encoded as 0 7256 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr) 7257 return false; 7258 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) { 7259 // Shifting by zero is accepted as a vanilla 'MOVr' 7260 MCInst TmpInst; 7261 TmpInst.setOpcode(ARM::MOVr); 7262 TmpInst.addOperand(Inst.getOperand(0)); 7263 TmpInst.addOperand(Inst.getOperand(1)); 7264 TmpInst.addOperand(Inst.getOperand(3)); 7265 TmpInst.addOperand(Inst.getOperand(4)); 7266 TmpInst.addOperand(Inst.getOperand(5)); 7267 Inst = TmpInst; 7268 return true; 7269 } 7270 return false; 7271 } 7272 case ARM::ANDrsi: 7273 case ARM::ORRrsi: 7274 case ARM::EORrsi: 7275 case ARM::BICrsi: 7276 case ARM::SUBrsi: 7277 case ARM::ADDrsi: { 7278 unsigned newOpc; 7279 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm()); 7280 if (SOpc == ARM_AM::rrx) return false; 7281 switch (Inst.getOpcode()) { 7282 default: llvm_unreachable("unexpected opcode!"); 7283 case ARM::ANDrsi: newOpc = ARM::ANDrr; break; 7284 case ARM::ORRrsi: newOpc = ARM::ORRrr; break; 7285 case ARM::EORrsi: newOpc = ARM::EORrr; break; 7286 case ARM::BICrsi: newOpc = ARM::BICrr; break; 7287 case ARM::SUBrsi: newOpc = ARM::SUBrr; break; 7288 case ARM::ADDrsi: newOpc = ARM::ADDrr; break; 7289 } 7290 // If the shift is by zero, use the non-shifted instruction definition. 7291 // The exception is for right shifts, where 0 == 32 7292 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 && 7293 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) { 7294 MCInst TmpInst; 7295 TmpInst.setOpcode(newOpc); 7296 TmpInst.addOperand(Inst.getOperand(0)); 7297 TmpInst.addOperand(Inst.getOperand(1)); 7298 TmpInst.addOperand(Inst.getOperand(2)); 7299 TmpInst.addOperand(Inst.getOperand(4)); 7300 TmpInst.addOperand(Inst.getOperand(5)); 7301 TmpInst.addOperand(Inst.getOperand(6)); 7302 Inst = TmpInst; 7303 return true; 7304 } 7305 return false; 7306 } 7307 case ARM::ITasm: 7308 case ARM::t2IT: { 7309 // The mask bits for all but the first condition are represented as 7310 // the low bit of the condition code value implies 't'. We currently 7311 // always have 1 implies 't', so XOR toggle the bits if the low bit 7312 // of the condition code is zero. 7313 MCOperand &MO = Inst.getOperand(1); 7314 unsigned Mask = MO.getImm(); 7315 unsigned OrigMask = Mask; 7316 unsigned TZ = CountTrailingZeros_32(Mask); 7317 if ((Inst.getOperand(0).getImm() & 1) == 0) { 7318 assert(Mask && TZ <= 3 && "illegal IT mask value!"); 7319 for (unsigned i = 3; i != TZ; --i) 7320 Mask ^= 1 << i; 7321 } 7322 MO.setImm(Mask); 7323 7324 // Set up the IT block state according to the IT instruction we just 7325 // matched. 7326 assert(!inITBlock() && "nested IT blocks?!"); 7327 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm()); 7328 ITState.Mask = OrigMask; // Use the original mask, not the updated one. 7329 ITState.CurPosition = 0; 7330 ITState.FirstCond = true; 7331 break; 7332 } 7333 case ARM::t2LSLrr: 7334 case ARM::t2LSRrr: 7335 case ARM::t2ASRrr: 7336 case ARM::t2SBCrr: 7337 case ARM::t2RORrr: 7338 case ARM::t2BICrr: 7339 { 7340 // Assemblers should use the narrow encodings of these instructions when permissible. 7341 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && 7342 isARMLowRegister(Inst.getOperand(2).getReg())) && 7343 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 7344 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) || 7345 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) && 7346 (!static_cast<ARMOperand*>(Operands[3])->isToken() || 7347 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) { 7348 unsigned NewOpc; 7349 switch (Inst.getOpcode()) { 7350 default: llvm_unreachable("unexpected opcode"); 7351 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break; 7352 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break; 7353 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break; 7354 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break; 7355 case ARM::t2RORrr: NewOpc = ARM::tROR; break; 7356 case ARM::t2BICrr: NewOpc = ARM::tBIC; break; 7357 } 7358 MCInst TmpInst; 7359 TmpInst.setOpcode(NewOpc); 7360 TmpInst.addOperand(Inst.getOperand(0)); 7361 TmpInst.addOperand(Inst.getOperand(5)); 7362 TmpInst.addOperand(Inst.getOperand(1)); 7363 TmpInst.addOperand(Inst.getOperand(2)); 7364 TmpInst.addOperand(Inst.getOperand(3)); 7365 TmpInst.addOperand(Inst.getOperand(4)); 7366 Inst = TmpInst; 7367 return true; 7368 } 7369 return false; 7370 } 7371 case ARM::t2ANDrr: 7372 case ARM::t2EORrr: 7373 case ARM::t2ADCrr: 7374 case ARM::t2ORRrr: 7375 { 7376 // Assemblers should use the narrow encodings of these instructions when permissible. 7377 // These instructions are special in that they are commutable, so shorter encodings 7378 // are available more often. 7379 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && 7380 isARMLowRegister(Inst.getOperand(2).getReg())) && 7381 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() || 7382 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) && 7383 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) || 7384 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) && 7385 (!static_cast<ARMOperand*>(Operands[3])->isToken() || 7386 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) { 7387 unsigned NewOpc; 7388 switch (Inst.getOpcode()) { 7389 default: llvm_unreachable("unexpected opcode"); 7390 case ARM::t2ADCrr: NewOpc = ARM::tADC; break; 7391 case ARM::t2ANDrr: NewOpc = ARM::tAND; break; 7392 case ARM::t2EORrr: NewOpc = ARM::tEOR; break; 7393 case ARM::t2ORRrr: NewOpc = ARM::tORR; break; 7394 } 7395 MCInst TmpInst; 7396 TmpInst.setOpcode(NewOpc); 7397 TmpInst.addOperand(Inst.getOperand(0)); 7398 TmpInst.addOperand(Inst.getOperand(5)); 7399 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) { 7400 TmpInst.addOperand(Inst.getOperand(1)); 7401 TmpInst.addOperand(Inst.getOperand(2)); 7402 } else { 7403 TmpInst.addOperand(Inst.getOperand(2)); 7404 TmpInst.addOperand(Inst.getOperand(1)); 7405 } 7406 TmpInst.addOperand(Inst.getOperand(3)); 7407 TmpInst.addOperand(Inst.getOperand(4)); 7408 Inst = TmpInst; 7409 return true; 7410 } 7411 return false; 7412 } 7413 } 7414 return false; 7415 } 7416 7417 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) { 7418 // 16-bit thumb arithmetic instructions either require or preclude the 'S' 7419 // suffix depending on whether they're in an IT block or not. 7420 unsigned Opc = Inst.getOpcode(); 7421 const MCInstrDesc &MCID = getInstDesc(Opc); 7422 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) { 7423 assert(MCID.hasOptionalDef() && 7424 "optionally flag setting instruction missing optional def operand"); 7425 assert(MCID.NumOperands == Inst.getNumOperands() && 7426 "operand count mismatch!"); 7427 // Find the optional-def operand (cc_out). 7428 unsigned OpNo; 7429 for (OpNo = 0; 7430 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands; 7431 ++OpNo) 7432 ; 7433 // If we're parsing Thumb1, reject it completely. 7434 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) 7435 return Match_MnemonicFail; 7436 // If we're parsing Thumb2, which form is legal depends on whether we're 7437 // in an IT block. 7438 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && 7439 !inITBlock()) 7440 return Match_RequiresITBlock; 7441 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && 7442 inITBlock()) 7443 return Match_RequiresNotITBlock; 7444 } 7445 // Some high-register supporting Thumb1 encodings only allow both registers 7446 // to be from r0-r7 when in Thumb2. 7447 else if (Opc == ARM::tADDhirr && isThumbOne() && 7448 isARMLowRegister(Inst.getOperand(1).getReg()) && 7449 isARMLowRegister(Inst.getOperand(2).getReg())) 7450 return Match_RequiresThumb2; 7451 // Others only require ARMv6 or later. 7452 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() && 7453 isARMLowRegister(Inst.getOperand(0).getReg()) && 7454 isARMLowRegister(Inst.getOperand(1).getReg())) 7455 return Match_RequiresV6; 7456 return Match_Success; 7457 } 7458 7459 static const char *getSubtargetFeatureName(unsigned Val); 7460 bool ARMAsmParser:: 7461 MatchAndEmitInstruction(SMLoc IDLoc, 7462 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 7463 MCStreamer &Out) { 7464 MCInst Inst; 7465 unsigned Kind; 7466 unsigned ErrorInfo; 7467 unsigned MatchResult; 7468 7469 MatchResult = MatchInstructionImpl(Operands, Kind, Inst, ErrorInfo); 7470 switch (MatchResult) { 7471 default: break; 7472 case Match_Success: 7473 // Context sensitive operand constraints aren't handled by the matcher, 7474 // so check them here. 7475 if (validateInstruction(Inst, Operands)) { 7476 // Still progress the IT block, otherwise one wrong condition causes 7477 // nasty cascading errors. 7478 forwardITPosition(); 7479 return true; 7480 } 7481 7482 // Some instructions need post-processing to, for example, tweak which 7483 // encoding is selected. Loop on it while changes happen so the 7484 // individual transformations can chain off each other. E.g., 7485 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8) 7486 while (processInstruction(Inst, Operands)) 7487 ; 7488 7489 // Only move forward at the very end so that everything in validate 7490 // and process gets a consistent answer about whether we're in an IT 7491 // block. 7492 forwardITPosition(); 7493 7494 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and 7495 // doesn't actually encode. 7496 if (Inst.getOpcode() == ARM::ITasm) 7497 return false; 7498 7499 Inst.setLoc(IDLoc); 7500 Out.EmitInstruction(Inst); 7501 return false; 7502 case Match_MissingFeature: { 7503 assert(ErrorInfo && "Unknown missing feature!"); 7504 // Special case the error message for the very common case where only 7505 // a single subtarget feature is missing (Thumb vs. ARM, e.g.). 7506 std::string Msg = "instruction requires:"; 7507 unsigned Mask = 1; 7508 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) { 7509 if (ErrorInfo & Mask) { 7510 Msg += " "; 7511 Msg += getSubtargetFeatureName(ErrorInfo & Mask); 7512 } 7513 Mask <<= 1; 7514 } 7515 return Error(IDLoc, Msg); 7516 } 7517 case Match_InvalidOperand: { 7518 SMLoc ErrorLoc = IDLoc; 7519 if (ErrorInfo != ~0U) { 7520 if (ErrorInfo >= Operands.size()) 7521 return Error(IDLoc, "too few operands for instruction"); 7522 7523 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 7524 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 7525 } 7526 7527 return Error(ErrorLoc, "invalid operand for instruction"); 7528 } 7529 case Match_MnemonicFail: 7530 return Error(IDLoc, "invalid instruction", 7531 ((ARMOperand*)Operands[0])->getLocRange()); 7532 case Match_RequiresNotITBlock: 7533 return Error(IDLoc, "flag setting instruction only valid outside IT block"); 7534 case Match_RequiresITBlock: 7535 return Error(IDLoc, "instruction only valid inside IT block"); 7536 case Match_RequiresV6: 7537 return Error(IDLoc, "instruction variant requires ARMv6 or later"); 7538 case Match_RequiresThumb2: 7539 return Error(IDLoc, "instruction variant requires Thumb2"); 7540 case Match_ImmRange0_15: { 7541 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 7542 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 7543 return Error(ErrorLoc, "immediate operand must be in the range [0,15]"); 7544 } 7545 } 7546 7547 llvm_unreachable("Implement any new match types added!"); 7548 } 7549 7550 /// parseDirective parses the arm specific directives 7551 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) { 7552 StringRef IDVal = DirectiveID.getIdentifier(); 7553 if (IDVal == ".word") 7554 return parseDirectiveWord(4, DirectiveID.getLoc()); 7555 else if (IDVal == ".thumb") 7556 return parseDirectiveThumb(DirectiveID.getLoc()); 7557 else if (IDVal == ".arm") 7558 return parseDirectiveARM(DirectiveID.getLoc()); 7559 else if (IDVal == ".thumb_func") 7560 return parseDirectiveThumbFunc(DirectiveID.getLoc()); 7561 else if (IDVal == ".code") 7562 return parseDirectiveCode(DirectiveID.getLoc()); 7563 else if (IDVal == ".syntax") 7564 return parseDirectiveSyntax(DirectiveID.getLoc()); 7565 else if (IDVal == ".unreq") 7566 return parseDirectiveUnreq(DirectiveID.getLoc()); 7567 else if (IDVal == ".arch") 7568 return parseDirectiveArch(DirectiveID.getLoc()); 7569 else if (IDVal == ".eabi_attribute") 7570 return parseDirectiveEabiAttr(DirectiveID.getLoc()); 7571 return true; 7572 } 7573 7574 /// parseDirectiveWord 7575 /// ::= .word [ expression (, expression)* ] 7576 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) { 7577 if (getLexer().isNot(AsmToken::EndOfStatement)) { 7578 for (;;) { 7579 const MCExpr *Value; 7580 if (getParser().ParseExpression(Value)) 7581 return true; 7582 7583 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/); 7584 7585 if (getLexer().is(AsmToken::EndOfStatement)) 7586 break; 7587 7588 // FIXME: Improve diagnostic. 7589 if (getLexer().isNot(AsmToken::Comma)) 7590 return Error(L, "unexpected token in directive"); 7591 Parser.Lex(); 7592 } 7593 } 7594 7595 Parser.Lex(); 7596 return false; 7597 } 7598 7599 /// parseDirectiveThumb 7600 /// ::= .thumb 7601 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) { 7602 if (getLexer().isNot(AsmToken::EndOfStatement)) 7603 return Error(L, "unexpected token in directive"); 7604 Parser.Lex(); 7605 7606 if (!isThumb()) 7607 SwitchMode(); 7608 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 7609 return false; 7610 } 7611 7612 /// parseDirectiveARM 7613 /// ::= .arm 7614 bool ARMAsmParser::parseDirectiveARM(SMLoc L) { 7615 if (getLexer().isNot(AsmToken::EndOfStatement)) 7616 return Error(L, "unexpected token in directive"); 7617 Parser.Lex(); 7618 7619 if (isThumb()) 7620 SwitchMode(); 7621 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 7622 return false; 7623 } 7624 7625 /// parseDirectiveThumbFunc 7626 /// ::= .thumbfunc symbol_name 7627 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) { 7628 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo(); 7629 bool isMachO = MAI.hasSubsectionsViaSymbols(); 7630 StringRef Name; 7631 bool needFuncName = true; 7632 7633 // Darwin asm has (optionally) function name after .thumb_func direction 7634 // ELF doesn't 7635 if (isMachO) { 7636 const AsmToken &Tok = Parser.getTok(); 7637 if (Tok.isNot(AsmToken::EndOfStatement)) { 7638 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) 7639 return Error(L, "unexpected token in .thumb_func directive"); 7640 Name = Tok.getIdentifier(); 7641 Parser.Lex(); // Consume the identifier token. 7642 needFuncName = false; 7643 } 7644 } 7645 7646 if (getLexer().isNot(AsmToken::EndOfStatement)) 7647 return Error(L, "unexpected token in directive"); 7648 7649 // Eat the end of statement and any blank lines that follow. 7650 while (getLexer().is(AsmToken::EndOfStatement)) 7651 Parser.Lex(); 7652 7653 // FIXME: assuming function name will be the line following .thumb_func 7654 // We really should be checking the next symbol definition even if there's 7655 // stuff in between. 7656 if (needFuncName) { 7657 Name = Parser.getTok().getIdentifier(); 7658 } 7659 7660 // Mark symbol as a thumb symbol. 7661 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name); 7662 getParser().getStreamer().EmitThumbFunc(Func); 7663 return false; 7664 } 7665 7666 /// parseDirectiveSyntax 7667 /// ::= .syntax unified | divided 7668 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) { 7669 const AsmToken &Tok = Parser.getTok(); 7670 if (Tok.isNot(AsmToken::Identifier)) 7671 return Error(L, "unexpected token in .syntax directive"); 7672 StringRef Mode = Tok.getString(); 7673 if (Mode == "unified" || Mode == "UNIFIED") 7674 Parser.Lex(); 7675 else if (Mode == "divided" || Mode == "DIVIDED") 7676 return Error(L, "'.syntax divided' arm asssembly not supported"); 7677 else 7678 return Error(L, "unrecognized syntax mode in .syntax directive"); 7679 7680 if (getLexer().isNot(AsmToken::EndOfStatement)) 7681 return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 7682 Parser.Lex(); 7683 7684 // TODO tell the MC streamer the mode 7685 // getParser().getStreamer().Emit???(); 7686 return false; 7687 } 7688 7689 /// parseDirectiveCode 7690 /// ::= .code 16 | 32 7691 bool ARMAsmParser::parseDirectiveCode(SMLoc L) { 7692 const AsmToken &Tok = Parser.getTok(); 7693 if (Tok.isNot(AsmToken::Integer)) 7694 return Error(L, "unexpected token in .code directive"); 7695 int64_t Val = Parser.getTok().getIntVal(); 7696 if (Val == 16) 7697 Parser.Lex(); 7698 else if (Val == 32) 7699 Parser.Lex(); 7700 else 7701 return Error(L, "invalid operand to .code directive"); 7702 7703 if (getLexer().isNot(AsmToken::EndOfStatement)) 7704 return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 7705 Parser.Lex(); 7706 7707 if (Val == 16) { 7708 if (!isThumb()) 7709 SwitchMode(); 7710 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 7711 } else { 7712 if (isThumb()) 7713 SwitchMode(); 7714 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 7715 } 7716 7717 return false; 7718 } 7719 7720 /// parseDirectiveReq 7721 /// ::= name .req registername 7722 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) { 7723 Parser.Lex(); // Eat the '.req' token. 7724 unsigned Reg; 7725 SMLoc SRegLoc, ERegLoc; 7726 if (ParseRegister(Reg, SRegLoc, ERegLoc)) { 7727 Parser.EatToEndOfStatement(); 7728 return Error(SRegLoc, "register name expected"); 7729 } 7730 7731 // Shouldn't be anything else. 7732 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { 7733 Parser.EatToEndOfStatement(); 7734 return Error(Parser.getTok().getLoc(), 7735 "unexpected input in .req directive."); 7736 } 7737 7738 Parser.Lex(); // Consume the EndOfStatement 7739 7740 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) 7741 return Error(SRegLoc, "redefinition of '" + Name + 7742 "' does not match original."); 7743 7744 return false; 7745 } 7746 7747 /// parseDirectiveUneq 7748 /// ::= .unreq registername 7749 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) { 7750 if (Parser.getTok().isNot(AsmToken::Identifier)) { 7751 Parser.EatToEndOfStatement(); 7752 return Error(L, "unexpected input in .unreq directive."); 7753 } 7754 RegisterReqs.erase(Parser.getTok().getIdentifier()); 7755 Parser.Lex(); // Eat the identifier. 7756 return false; 7757 } 7758 7759 /// parseDirectiveArch 7760 /// ::= .arch token 7761 bool ARMAsmParser::parseDirectiveArch(SMLoc L) { 7762 return true; 7763 } 7764 7765 /// parseDirectiveEabiAttr 7766 /// ::= .eabi_attribute int, int 7767 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) { 7768 return true; 7769 } 7770 7771 extern "C" void LLVMInitializeARMAsmLexer(); 7772 7773 /// Force static initialization. 7774 extern "C" void LLVMInitializeARMAsmParser() { 7775 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget); 7776 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget); 7777 LLVMInitializeARMAsmLexer(); 7778 } 7779 7780 #define GET_REGISTER_MATCHER 7781 #define GET_SUBTARGET_FEATURE_NAME 7782 #define GET_MATCHER_IMPLEMENTATION 7783 #include "ARMGenAsmMatcher.inc" 7784
