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      1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file declares the ARM specific subclass of TargetSubtargetInfo.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #ifndef ARMSUBTARGET_H
     15 #define ARMSUBTARGET_H
     16 
     17 #include "MCTargetDesc/ARMMCTargetDesc.h"
     18 #include "llvm/Target/TargetSubtargetInfo.h"
     19 #include "llvm/MC/MCInstrItineraries.h"
     20 #include "llvm/ADT/Triple.h"
     21 #include <string>
     22 
     23 #define GET_SUBTARGETINFO_HEADER
     24 #include "ARMGenSubtargetInfo.inc"
     25 
     26 namespace llvm {
     27 class GlobalValue;
     28 class StringRef;
     29 
     30 class ARMSubtarget : public ARMGenSubtargetInfo {
     31 protected:
     32   enum ARMProcFamilyEnum {
     33     Others, CortexA8, CortexA9
     34   };
     35 
     36   /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
     37   ARMProcFamilyEnum ARMProcFamily;
     38 
     39   /// HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6T2Ops, HasV7Ops -
     40   /// Specify whether target support specific ARM ISA variants.
     41   bool HasV4TOps;
     42   bool HasV5TOps;
     43   bool HasV5TEOps;
     44   bool HasV6Ops;
     45   bool HasV6T2Ops;
     46   bool HasV7Ops;
     47 
     48   /// HasVFPv2, HasVFPv3, HasVFPv4, HasNEON - Specify what
     49   /// floating point ISAs are supported.
     50   bool HasVFPv2;
     51   bool HasVFPv3;
     52   bool HasVFPv4;
     53   bool HasNEON;
     54 
     55   /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
     56   /// specified. Use the method useNEONForSinglePrecisionFP() to
     57   /// determine if NEON should actually be used.
     58   bool UseNEONForSinglePrecisionFP;
     59 
     60   /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
     61   /// whether the FP VML[AS] instructions are slow (if so, don't use them).
     62   bool SlowFPVMLx;
     63 
     64   /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
     65   /// forwarding to allow mul + mla being issued back to back.
     66   bool HasVMLxForwarding;
     67 
     68   /// SlowFPBrcc - True if floating point compare + branch is slow.
     69   bool SlowFPBrcc;
     70 
     71   /// InThumbMode - True if compiling for Thumb, false for ARM.
     72   bool InThumbMode;
     73 
     74   /// HasThumb2 - True if Thumb2 instructions are supported.
     75   bool HasThumb2;
     76 
     77   /// IsMClass - True if the subtarget belongs to the 'M' profile of CPUs -
     78   /// v6m, v7m for example.
     79   bool IsMClass;
     80 
     81   /// NoARM - True if subtarget does not support ARM mode execution.
     82   bool NoARM;
     83 
     84   /// PostRAScheduler - True if using post-register-allocation scheduler.
     85   bool PostRAScheduler;
     86 
     87   /// IsR9Reserved - True if R9 is a not available as general purpose register.
     88   bool IsR9Reserved;
     89 
     90   /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
     91   /// imms (including global addresses).
     92   bool UseMovt;
     93 
     94   /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
     95   /// must be able to synthesize call stubs for interworking between ARM and
     96   /// Thumb.
     97   bool SupportsTailCall;
     98 
     99   /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
    100   /// only so far)
    101   bool HasFP16;
    102 
    103   /// HasD16 - True if subtarget is limited to 16 double precision
    104   /// FP registers for VFPv3.
    105   bool HasD16;
    106 
    107   /// HasHardwareDivide - True if subtarget supports [su]div
    108   bool HasHardwareDivide;
    109 
    110   /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
    111   /// instructions.
    112   bool HasT2ExtractPack;
    113 
    114   /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
    115   /// instructions.
    116   bool HasDataBarrier;
    117 
    118   /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
    119   /// over 16-bit ones.
    120   bool Pref32BitThumb;
    121 
    122   /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
    123   /// that partially update CPSR and add false dependency on the previous
    124   /// CPSR setting instruction.
    125   bool AvoidCPSRPartialUpdate;
    126 
    127   /// HasRAS - Some processors perform return stack prediction. CodeGen should
    128   /// avoid issue "normal" call instructions to callees which do not return.
    129   bool HasRAS;
    130 
    131   /// HasMPExtension - True if the subtarget supports Multiprocessing
    132   /// extension (ARMv7 only).
    133   bool HasMPExtension;
    134 
    135   /// FPOnlySP - If true, the floating point unit only supports single
    136   /// precision.
    137   bool FPOnlySP;
    138 
    139   /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
    140   /// accesses for some types.  For details, see
    141   /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
    142   bool AllowsUnalignedMem;
    143 
    144   /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
    145   /// and such) instructions in Thumb2 code.
    146   bool Thumb2DSP;
    147 
    148   /// stackAlignment - The minimum alignment known to hold of the stack frame on
    149   /// entry to the function and which must be maintained by every function.
    150   unsigned stackAlignment;
    151 
    152   /// CPUString - String name of used CPU.
    153   std::string CPUString;
    154 
    155   /// TargetTriple - What processor and OS we're targeting.
    156   Triple TargetTriple;
    157 
    158   /// SchedModel - Processor specific instruction costs.
    159   const MCSchedModel *SchedModel;
    160 
    161   /// Selected instruction itineraries (one entry per itinerary class.)
    162   InstrItineraryData InstrItins;
    163 
    164  public:
    165   enum {
    166     isELF, isDarwin
    167   } TargetType;
    168 
    169   enum {
    170     ARM_ABI_APCS,
    171     ARM_ABI_AAPCS // ARM EABI
    172   } TargetABI;
    173 
    174   /// This constructor initializes the data members to match that
    175   /// of the specified triple.
    176   ///
    177   ARMSubtarget(const std::string &TT, const std::string &CPU,
    178                const std::string &FS);
    179 
    180   /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
    181   /// that still makes it profitable to inline the call.
    182   unsigned getMaxInlineSizeThreshold() const {
    183     // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
    184     // Change this once Thumb1 ldmia / stmia support is added.
    185     return isThumb1Only() ? 0 : 64;
    186   }
    187   /// ParseSubtargetFeatures - Parses features string setting specified
    188   /// subtarget options.  Definition of function is auto generated by tblgen.
    189   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
    190 
    191   void computeIssueWidth();
    192 
    193   bool hasV4TOps()  const { return HasV4TOps;  }
    194   bool hasV5TOps()  const { return HasV5TOps;  }
    195   bool hasV5TEOps() const { return HasV5TEOps; }
    196   bool hasV6Ops()   const { return HasV6Ops;   }
    197   bool hasV6T2Ops() const { return HasV6T2Ops; }
    198   bool hasV7Ops()   const { return HasV7Ops;  }
    199 
    200   bool isCortexA8() const { return ARMProcFamily == CortexA8; }
    201   bool isCortexA9() const { return ARMProcFamily == CortexA9; }
    202   bool isCortexM3() const { return CPUString == "cortex-m3"; }
    203 
    204   bool hasARMOps() const { return !NoARM; }
    205 
    206   bool hasVFP2() const { return HasVFPv2; }
    207   bool hasVFP3() const { return HasVFPv3; }
    208   bool hasVFP4() const { return HasVFPv4; }
    209   bool hasNEON() const { return HasNEON;  }
    210   bool useNEONForSinglePrecisionFP() const {
    211     return hasNEON() && UseNEONForSinglePrecisionFP; }
    212 
    213   bool hasDivide() const { return HasHardwareDivide; }
    214   bool hasT2ExtractPack() const { return HasT2ExtractPack; }
    215   bool hasDataBarrier() const { return HasDataBarrier; }
    216   bool useFPVMLx() const { return !SlowFPVMLx; }
    217   bool hasVMLxForwarding() const { return HasVMLxForwarding; }
    218   bool isFPBrccSlow() const { return SlowFPBrcc; }
    219   bool isFPOnlySP() const { return FPOnlySP; }
    220   bool prefers32BitThumb() const { return Pref32BitThumb; }
    221   bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
    222   bool hasRAS() const { return HasRAS; }
    223   bool hasMPExtension() const { return HasMPExtension; }
    224   bool hasThumb2DSP() const { return Thumb2DSP; }
    225 
    226   bool hasFP16() const { return HasFP16; }
    227   bool hasD16() const { return HasD16; }
    228 
    229   const Triple &getTargetTriple() const { return TargetTriple; }
    230 
    231   bool isTargetIOS() const { return TargetTriple.getOS() == Triple::IOS; }
    232   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
    233   bool isTargetNaCl() const {
    234     return TargetTriple.getOS() == Triple::NativeClient;
    235   }
    236   bool isTargetELF() const { return !isTargetDarwin(); }
    237 
    238   bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
    239   bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
    240 
    241   bool isThumb() const { return InThumbMode; }
    242   bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
    243   bool isThumb2() const { return InThumbMode && HasThumb2; }
    244   bool hasThumb2() const { return HasThumb2; }
    245   bool isMClass() const { return IsMClass; }
    246   bool isARClass() const { return !IsMClass; }
    247 
    248   bool isR9Reserved() const { return IsR9Reserved; }
    249 
    250   bool useMovt() const { return UseMovt && hasV6T2Ops(); }
    251   bool supportsTailCall() const { return SupportsTailCall; }
    252 
    253   bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
    254 
    255   const std::string & getCPUString() const { return CPUString; }
    256 
    257   unsigned getMispredictionPenalty() const;
    258 
    259   /// enablePostRAScheduler - True at 'More' optimization.
    260   bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
    261                              TargetSubtargetInfo::AntiDepBreakMode& Mode,
    262                              RegClassVector& CriticalPathRCs) const;
    263 
    264   /// getInstrItins - Return the instruction itineraies based on subtarget
    265   /// selection.
    266   const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
    267 
    268   /// getStackAlignment - Returns the minimum alignment known to hold of the
    269   /// stack frame on entry to the function and which must be maintained by every
    270   /// function for this subtarget.
    271   unsigned getStackAlignment() const { return stackAlignment; }
    272 
    273   /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
    274   /// symbol.
    275   bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
    276 };
    277 } // End llvm namespace
    278 
    279 #endif  // ARMSUBTARGET_H
    280