/external/llvm/lib/Target/ARM/ |
ARMSelectionDAGInfo.h | 22 namespace ARM_AM { 25 default: return ARM_AM::no_shift; 26 case ISD::SHL: return ARM_AM::lsl; 27 case ISD::SRL: return ARM_AM::lsr; 28 case ISD::SRA: return ARM_AM::asr; 29 case ISD::ROTR: return ARM_AM::ror; 33 //case ARMISD::RRX: return ARM_AM::rrx; 36 } // end namespace ARM_AM
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ARMLoadStoreOptimizer.cpp | 137 static int getLoadStoreMultipleOpcode(int Opcode, ARM_AM::AMSubMode Mode) { 144 case ARM_AM::ia: return ARM::LDMIA; 145 case ARM_AM::da: return ARM::LDMDA; 146 case ARM_AM::db: return ARM::LDMDB; 147 case ARM_AM::ib: return ARM::LDMIB; 153 case ARM_AM::ia: return ARM::STMIA; 154 case ARM_AM::da: return ARM::STMDA; 155 case ARM_AM::db: return ARM::STMDB; 156 case ARM_AM::ib: return ARM::STMIB; 163 case ARM_AM::ia: return ARM::t2LDMIA [all...] |
ARMISelDAGToDAG.cpp | 92 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt); 179 return ARM_AM::getSOImmVal(Imm) != -1; 183 return ARM_AM::getSOImmVal(~Imm) != -1; 187 return ARM_AM::getT2SOImmVal(Imm) != -1; 191 return ARM_AM::getT2SOImmVal(~Imm) != -1; 375 ARM_AM::ShiftOpc ShOpcVal, 382 return ShOpcVal == ARM_AM::lsl && ShAmt == 2; 392 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); 396 if (ShOpcVal == ARM_AM::no_shift) return false [all...] |
Thumb2InstrInfo.cpp | 189 ARM_AM::getT2SOImmVal(NumBytes) == -1) { 249 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) { 254 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt); 256 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 && 262 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) { 271 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt); 273 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 && 427 if (ARM_AM::getT2SOImmVal(Offset) != -1) { 453 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt); 458 assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 & [all...] |
ARMCodeEmitter.cpp | 430 switch (ARM_AM::getAM2ShiftOpc(Imm)) { 432 case ARM_AM::asr: return 2; 433 case ARM_AM::lsl: return 0; 434 case ARM_AM::lsr: return 1; 435 case ARM_AM::ror: 436 case ARM_AM::rrx: return 3; 776 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) && 778 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm()); 779 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm()); [all...] |
ARMJITInfo.cpp | 312 int SoImmVal = ARM_AM::getSOImmVal(ResultPtr); 314 *((intptr_t*)RelocPos) |= (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1) 316 *((intptr_t*)RelocPos) |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
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ARMBaseInstrInfo.cpp | 161 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 162 unsigned Amt = ARM_AM::getAM2Offset(OffImm); 164 if (ARM_AM::getSOImmVal(Amt) == -1) 173 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 174 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 187 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 188 unsigned Amt = ARM_AM::getAM3Offset(OffImm) [all...] |
ARMBaseRegisterInfo.cpp | 819 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); 820 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub) 827 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm()); 828 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 834 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm()); 835 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) [all...] |
ARMExpandPseudoInsts.cpp | 633 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal); 634 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal); [all...] |
ARMFastISel.cpp | 173 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy); 521 Imm = ARM_AM::getFP64Imm(Val); 524 Imm = ARM_AM::getFP32Imm(Val); 575 bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) : 576 (ARM_AM::getSOImmVal(Imm) != -1); [all...] |
ARMISelLowering.cpp | [all...] |
ARMFrameLowering.cpp | 714 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift)); [all...] |
/external/llvm/lib/Target/ARM/InstPrinter/ |
ARMInstPrinter.cpp | 84 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); 92 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); 103 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); 110 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { 115 O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())); 272 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()) [all...] |
/external/llvm/lib/Target/ARM/MCTargetDesc/ |
ARMAddressingModes.h | 25 /// ARM_AM - ARM Addressing Mode Stuff 26 namespace ARM_AM { 48 case ARM_AM::asr: return "asr"; 49 case ARM_AM::lsl: return "lsl"; 50 case ARM_AM::lsr: return "lsr"; 51 case ARM_AM::ror: return "ror"; 52 case ARM_AM::rrx: return "rrx"; 59 case ARM_AM::asr: return 2; 60 case ARM_AM::lsl: return 0; 61 case ARM_AM::lsr: return 1 [all...] |
ARMMCCodeEmitter.cpp | 171 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); 174 case ARM_AM::da: return 0; 175 case ARM_AM::ia: return 1; 176 case ARM_AM::db: return 2; 177 case ARM_AM::ib: return 3; 182 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { 184 case ARM_AM::no_shift: 185 case ARM_AM::lsl: return 0; 186 case ARM_AM::lsr: return 1 [all...] |
ARMAsmBackend.cpp | 328 if (Ctx && ARM_AM::getSOImmVal(Value) == -1) 331 return ARM_AM::getSOImmVal(Value) | (opc << 21);
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/external/llvm/lib/Target/ARM/AsmParser/ |
ARMAsmParser.cpp | 101 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, 372 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg 382 ARM_AM::ShiftOpc ShiftTy; 391 ARM_AM::ShiftOpc ShiftTy; 397 ARM_AM::ShiftOpc ShiftTy; 556 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 812 return ARM_AM::getSOImmVal(Value) != -1; 819 return ARM_AM::getSOImmVal(~Value) != -1; 827 return ARM_AM::getSOImmVal(Value) == -1 && 828 ARM_AM::getSOImmVal(-Value) != -1 [all...] |
/external/llvm/lib/Target/ARM/Disassembler/ |
ARMDisassembler.cpp | [all...] |