| /external/llvm/include/llvm/Transforms/Utils/ |
| AddrModeMatcher.h | 37 Value *BaseReg;
39 ExtAddrMode() : BaseReg(0), ScaledReg(0) {}
44 return (BaseReg == O.BaseReg) && (ScaledReg == O.ScaledReg) &&
|
| /external/llvm/lib/Transforms/Utils/ |
| AddrModeMatcher.cpp | 42 if (BaseReg) {
45 WriteAsOperand(OS, BaseReg, /*PrintType=*/false);
277 AddrMode.BaseReg = AddrInst->getOperand(0);
290 AddrMode.BaseReg = AddrInst->getOperand(0);
358 AddrMode.BaseReg = Addr;
363 AddrMode.BaseReg = 0;
516 // BaseReg and ScaleReg (global addresses are always available, as are any
518 Value *BaseReg = AMAfter.BaseReg, *ScaledReg = AMAfter.ScaledReg;
520 // If the BaseReg or ScaledReg was referenced by the previous addrmode, thei
[all...] |
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86ATTInstPrinter.cpp | 138 const MCOperand &BaseReg = MI->getOperand(Op);
151 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
158 if (IndexReg.getReg() || BaseReg.getReg()) {
160 if (BaseReg.getReg())
|
| X86IntelInstPrinter.cpp | 129 const MCOperand &BaseReg = MI->getOperand(Op);
144 if (BaseReg.getReg()) {
164 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
|
| /external/llvm/lib/CodeGen/ |
| LocalStackSlotAllocation.cpp | 290 unsigned BaseReg = 0;
310 BaseReg = RegOffset.first;
319 BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
321 DEBUG(dbgs() << " Materializing base register " << BaseReg <<
328 TRI->materializeFrameBaseRegister(Entry, BaseReg, FrameIdx,
339 std::pair<unsigned, int64_t>(BaseReg, BaseOffset));
343 assert(BaseReg != 0 && "Unable to allocate virtual base register!");
347 TRI->resolveFrameIndex(I, BaseReg, Offset);
|
| /external/llvm/lib/Target/ARM/ |
| Thumb1RegisterInfo.cpp | 86 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
93 unsigned DestReg, unsigned BaseReg,
100 (BaseReg != 0 && !isARMLowRegister(BaseReg));
112 assert(BaseReg == ARM::SP && "Unexpected!");
135 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
137 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
166 /// a destreg = basereg + immediate in Thumb code.
170 unsigned DestReg, unsigned BaseReg,
186 if (DestReg == BaseReg && BaseReg == ARM::SP)
[all...] |
| Thumb2InstrInfo.cpp | 179 unsigned DestReg, unsigned BaseReg, int NumBytes,
187 if (DestReg != ARM::SP && DestReg != BaseReg &&
209 .addReg(BaseReg, RegState::Kill)
216 .addReg(BaseReg, RegState::Kill)
227 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
230 .addReg(BaseReg).setMIFlags(MIFlags));
231 BaseReg = ARM::SP;
236 if (BaseReg == ARM::SP) {
242 .addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags));
260 assert(DestReg != ARM::SP && BaseReg != ARM::SP)
[all...] |
| Thumb1RegisterInfo.h | 58 unsigned BaseReg, int64_t Offset) const;
|
| ARMBaseRegisterInfo.h | 142 unsigned BaseReg, int FrameIdx,
145 unsigned BaseReg, int64_t Offset) const;
|
| ARMBaseInstrInfo.h | 374 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
378 unsigned DestReg, unsigned BaseReg, int NumBytes,
384 unsigned DestReg, unsigned BaseReg, int NumBytes,
389 unsigned DestReg, unsigned BaseReg,
|
| ARMLoadStoreOptimizer.cpp | [all...] |
| Thumb2SizeReduction.cpp | 127 // ARM::t2STM (with no basereg writeback) has no Thumb1 equivalent
380 unsigned BaseReg = MI->getOperand(0).getReg();
381 if (!isARMLowRegister(BaseReg) || Entry.WideOpc != ARM::t2LDMIA)
388 if (MI->getOperand(i).getReg() == BaseReg) {
402 unsigned BaseReg = MI->getOperand(1).getReg();
403 if (BaseReg != ARM::SP)
416 unsigned BaseReg = MI->getOperand(1).getReg();
417 if (BaseReg == ARM::SP &&
422 } else if (!isARMLowRegister(BaseReg) ||
[all...] |
| ARMBaseRegisterInfo.cpp | [all...] |
| ARMConstantIslandPass.cpp | [all...] |
| ARMBaseInstrInfo.cpp | 154 unsigned BaseReg = Base.getReg();
170 .addReg(BaseReg).addImm(Amt)
177 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
182 .addReg(BaseReg).addReg(OffReg)
193 .addReg(BaseReg).addImm(Amt)
198 .addReg(BaseReg).addReg(OffReg)
220 .addReg(BaseReg).addImm(0).addImm(Pred);
224 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
[all...] |
| ARMISelDAGToDAG.cpp | 169 SDValue &BaseReg, SDValue &Opc);
386 SDValue &BaseReg,
398 BaseReg = N.getOperand(0);
409 SDValue &BaseReg,
422 BaseReg = N.getOperand(0);
[all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 191 unsigned BaseReg;
240 return Mem.BaseReg;
469 Res->Mem.BaseReg = 0;
478 unsigned BaseReg, unsigned IndexReg,
483 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
491 Res->Mem.BaseReg = BaseReg;
502 unsigned basereg = is64BitMode() ? X86::RSI : X86::ESI; local
508 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0)
512 unsigned basereg = is64BitMode() ? X86::RDI : X86::EDI; local
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 166 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
169 if ((BaseReg.getReg() != 0 &&
170 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
181 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
184 if ((BaseReg.getReg() != 0 &&
185 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
196 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
199 if ((BaseReg.getReg() != 0 &&
200 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
306 unsigned BaseReg = Base.getReg()
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86CodeEmitter.cpp | 481 unsigned BaseReg = Base.getReg();
484 if (BaseReg == X86::RIP ||
499 // If no BaseReg, issue a RIP relative instruction only if the MCE can
503 if (BaseReg != 0 && BaseReg != X86::RIP)
504 BaseRegNo = X86_MC::getX86RegNum(BaseReg);
514 (!Is64BitMode || BaseReg != 0)) {
515 if (BaseReg == 0 || // [disp32] in X86-32 mode
516 BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
550 if (BaseReg == 0)
[all...] |
| X86AsmPrinter.cpp | 312 const MachineOperand &BaseReg = MI->getOperand(Op);
317 bool HasBaseReg = BaseReg.getReg() != 0;
319 BaseReg.getReg() == X86::RIP)
|
| X86InstrInfo.cpp | [all...] |
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 695 /// BaseReg to be a pointer to FrameIdx before insertion point I.
697 unsigned BaseReg, int FrameIdx,
706 unsigned BaseReg, int64_t Offset) const {
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| LoopStrengthReduce.cpp | 911 const SCEV *BaseReg = *I;
912 if (VisitedRegs.count(BaseReg)) {
916 RatePrimaryRegister(BaseReg, Regs, L, SE, DT, LoserRegs);
[all...] |
| CodeGenPrepare.cpp | [all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 192 unsigned BaseReg = MI->getOperand(0).getReg();
194 if (MI->getOperand(i).getReg() == BaseReg)
201 O << '\t' << getRegisterName(BaseReg);
[all...] |
