| /external/llvm/include/llvm/MC/ |
| MCInstrItineraries.h | 201 /// index DefIdx can be bypassed when it's read by an instruction of
203 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx,
207 if ((FirstDefIdx + DefIdx) >= LastDefIdx)
209 if (Forwardings[FirstDefIdx + DefIdx] == 0)
217 return Forwardings[FirstDefIdx + DefIdx] ==
224 int getOperandLatency(unsigned DefClass, unsigned DefIdx,
229 int DefCycle = getOperandCycle(DefClass, DefIdx);
239 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx))
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.h | 135 unsigned DefIdx;
153 return DefIdx-1;
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| ScheduleDAGSDNodes.cpp | 547 DefIdx = 0;
553 : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) {
561 for (;DefIdx < NodeNumDefs; ++DefIdx) {
562 if (!Node->hasAnyUseOfValue(DefIdx))
564 ValueType = Node->getValueType(DefIdx);
565 ++DefIdx;
627 unsigned DefIdx = Use->getOperand(OpIdx).getResNo();
631 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
[all...] |
| InstrEmitter.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.h | 222 const MachineInstr *DefMI, unsigned DefIdx,
226 SDNode *DefNode, unsigned DefIdx,
230 const MachineInstr *DefMI, unsigned DefIdx,
244 unsigned DefIdx, unsigned DefAlign) const;
248 unsigned DefIdx, unsigned DefAlign) const;
259 unsigned DefIdx, unsigned DefAlign,
272 const MachineInstr *DefMI, unsigned DefIdx,
275 const MachineInstr *DefMI, unsigned DefIdx) const;
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| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | [all...] |
| /external/llvm/lib/CodeGen/ |
| TargetInstrInfoImpl.cpp | 517 SDNode *DefNode, unsigned DefIdx,
527 return ItinData->getOperandCycle(DefClass, DefIdx);
529 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
587 unsigned DefIdx) const {
592 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
600 const MachineInstr *DefMI, unsigned DefIdx,
604 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
647 /// to call getOperandLatency(). For most subtargets, we don't need DefIdx or
651 const MachineInstr *DefMI, unsigned DefIdx,
663 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx)
[all...] |
| LiveRangeEdit.cpp | 115 SlotIndex DefIdx;
117 DefIdx = LIS.getInstructionIndex(RM.OrigMI);
119 DefIdx = RM.ParentVNI->def;
120 RM.OrigMI = LIS.getInstructionFromIndex(DefIdx);
129 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
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| LiveRangeCalc.cpp | 90 unsigned DefIdx;
94 } else if (MI->isRegTiedToDefOperand(I.getOperandNo(), &DefIdx)) {
97 if (MI->getOperand(DefIdx).isEarlyClobber())
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| MachineInstr.cpp | 733 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
734 if (DefIdx != -1)
735 tieOperands(DefIdx, OpNo);
[all...] |
| MachineVerifier.cpp | 859 unsigned DefIdx;
861 MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
862 Reg != MI->getOperand(DefIdx).getReg())
[all...] |
| RegisterCoalescer.cpp | 569 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
570 assert(DefIdx != -1);
572 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
672 SlotIndex DefIdx = UseIdx.getRegSlot();
673 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
676 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
677 assert(DVNI->def == DefIdx);
[all...] |
| InlineSpiller.cpp | 888 SlotIndex DefIdx = Edit->rematerializeAt(*MI->getParent(), MI, NewLI.reg, RM,
890 DEBUG(dbgs() << "\tremat: " << DefIdx << '\t
[all...] |
| MachineLICM.cpp | 200 bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
[all...] |
| RegAllocFast.cpp | 725 unsigned DefIdx = 0;
726 if (!MI->isRegTiedToDefOperand(i, &DefIdx)) continue;
728 << DefIdx << ".\n");
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 372 const MachineInstr *DefMI, unsigned DefIdx,
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| X86InstrInfo.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 787 /// tieOperands - Add a tie between the register operands at DefIdx an
[all...] |
