| /external/llvm/lib/CodeGen/ |
| CallingConvLower.cpp | 67 CCState::AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
69 unsigned NumArgs = Ins.size();
72 MVT ArgVT = Ins[i].VT;
73 ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
155 void CCState::AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
157 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
158 MVT VT = Ins[i].VT;
159 ISD::ArgFlagsTy Flags = Ins[i].Flags;
|
| RegAllocGreedy.cpp | 707 unsigned Ins = 0;
712 BC.Entry = SpillPlacement::MustSpill, ++Ins;
714 BC.Entry = SpillPlacement::PrefSpill, ++Ins;
716 ++Ins;
722 BC.Exit = SpillPlacement::MustSpill, ++Ins;
724 BC.Exit = SpillPlacement::PrefSpill, ++Ins;
726 ++Ins;
730 if (Ins)
731 StaticCost += Ins * SpillPlacer->getBlockFrequency(BC.Number);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.cpp | 67 &Ins,
70 unsigned NumArgs = Ins.size();
81 EVT ArgVT = Ins[i].VT;
82 ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
180 Hexagon_CCState::AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
184 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
185 EVT VT = Ins[i].VT;
|
| HexagonISelLowering.h | 79 const SmallVectorImpl<ISD::InputArg> &Ins,
94 const SmallVectorImpl<ISD::InputArg> &Ins,
104 const SmallVectorImpl<ISD::InputArg> &Ins,
|
| HexagonCallingConvLower.h | 80 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
102 void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 130 const SmallVectorImpl<ISD::InputArg> &Ins,
137 const SmallVectorImpl<ISD::InputArg> &Ins,
144 const SmallVectorImpl<ISD::InputArg> &Ins,
151 const SmallVectorImpl<ISD::InputArg> &Ins,
|
| MSP430ISelLowering.cpp | 249 &Ins,
260 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
262 if (Ins.empty())
275 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
291 Outs, OutVals, Ins, dl, DAG, InVals);
306 &Ins,
319 CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430);
446 const SmallVectorImpl<ISD::InputArg> &Ins,
558 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl
[all...] |
| /external/llvm/lib/Transforms/IPO/ |
| PartialInlining.cpp | 93 BasicBlock::iterator Ins = newReturnBlock->begin();
98 PHINode* retPhi = PHINode::Create(OldPhi->getType(), 2, "", Ins);
100 Ins = newReturnBlock->getFirstNonPHI();
|
| IPConstantPropagation.cpp | 250 Instruction *Ins = cast<Instruction>(*I);
257 if (ExtractValueInst *EV = dyn_cast<ExtractValueInst>(Ins))
270 Ins->replaceAllUsesWith(New);
271 Ins->eraseFromParent();
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.h | 115 const SmallVectorImpl<ISD::InputArg> &Ins,
130 const SmallVectorImpl<ISD::InputArg> &Ins,
|
| MBlazeISelLowering.cpp | 690 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
831 if (!Ins.empty())
837 Ins, dl, DAG, InVals);
844 bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins,
852 CCInfo.AnalyzeCallResult(Ins, RetCC_MBlaze);
874 const SmallVectorImpl<ISD::InputArg> &Ins,
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 387 const SmallVectorImpl<ISD::InputArg> &Ins,
431 const SmallVectorImpl<ISD::InputArg> &Ins,
442 const SmallVectorImpl<ISD::InputArg> &Ins,
448 const SmallVectorImpl<ISD::InputArg> &Ins,
472 const SmallVectorImpl<ISD::InputArg> &Ins,
478 const SmallVectorImpl<ISD::InputArg> &Ins,
487 const SmallVectorImpl<ISD::InputArg> &Ins,
495 const SmallVectorImpl<ISD::InputArg> &Ins,
|
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.h | 114 const SmallVectorImpl<ISD::InputArg> &Ins,
122 const SmallVectorImpl<ISD::InputArg> &Ins,
127 const SmallVectorImpl<ISD::InputArg> &Ins,
172 const SmallVectorImpl<ISD::InputArg> &Ins,
|
| XCoreISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 448 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
605 if (Ins.size() > 0) {
699 DAG.getConstant(isABI ? ((Ins.size()==0) ? 0 : 1)
750 if (Ins.size() > 0) {
753 for (unsigned i=0,e=Ins.size(); i!=e; ++i) {
754 unsigned sz = Ins[i].VT.getSizeInBits();
755 if (Ins[i].VT.isInteger() && (sz < 8)) sz = 8;
757 LoadRetVTs.push_back(Ins[i].VT);
776 assert(Ins.size() == resvtparts.size() &
[all...] |
| NVPTXISelLowering.h | 104 const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl,
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.h | 74 const SmallVectorImpl<ISD::InputArg> &Ins,
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.h | 82 Ins,
128 const SmallVectorImpl<ISD::InputArg> &Ins,
158 const SmallVectorImpl<ISD::InputArg> &Ins,
|
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.h | 75 std::pair<CompMap::iterator, bool> Ins =
77 return (Ins.second || Ins.first->second == B) ? 0 : Ins.first->second;
|
| /external/llvm/include/llvm/CodeGen/ |
| CallingConvLower.h | 196 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
223 void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
|
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.h | 457 const SmallVectorImpl<ISD::InputArg> &Ins,
464 const SmallVectorImpl<ISD::InputArg> &Ins,
492 const SmallVectorImpl<ISD::InputArg> &Ins,
|
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.h | 156 const SmallVectorImpl<ISD::InputArg> &Ins,
|
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.h | 723 const SmallVectorImpl<ISD::InputArg> &Ins,
749 const SmallVectorImpl<ISD::InputArg> &Ins,
[all...] |
| /external/llvm/include/llvm/Transforms/Utils/ |
| SSAUpdaterImpl.h | 71 SmallVectorImpl<PhiT*> *Ins) :
72 Updater(U), AvailableVals(A), InsertedPHIs(Ins) { }
|
