1 //===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines structures to encapsulate information gleaned from the 11 // target register and register class definitions. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef CODEGEN_REGISTERS_H 16 #define CODEGEN_REGISTERS_H 17 18 #include "SetTheory.h" 19 #include "llvm/TableGen/Record.h" 20 #include "llvm/CodeGen/ValueTypes.h" 21 #include "llvm/ADT/ArrayRef.h" 22 #include "llvm/ADT/BitVector.h" 23 #include "llvm/ADT/DenseMap.h" 24 #include "llvm/ADT/SetVector.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include <cstdlib> 27 #include <map> 28 #include <string> 29 #include <set> 30 #include <vector> 31 32 namespace llvm { 33 class CodeGenRegBank; 34 35 /// CodeGenSubRegIndex - Represents a sub-register index. 36 class CodeGenSubRegIndex { 37 Record *const TheDef; 38 std::string Name; 39 std::string Namespace; 40 41 public: 42 const unsigned EnumValue; 43 44 CodeGenSubRegIndex(Record *R, unsigned Enum); 45 CodeGenSubRegIndex(StringRef N, StringRef Nspace, unsigned Enum); 46 47 const std::string &getName() const { return Name; } 48 const std::string &getNamespace() const { return Namespace; } 49 std::string getQualifiedName() const; 50 51 // Order CodeGenSubRegIndex pointers by EnumValue. 52 struct Less { 53 bool operator()(const CodeGenSubRegIndex *A, 54 const CodeGenSubRegIndex *B) const { 55 assert(A && B); 56 return A->EnumValue < B->EnumValue; 57 } 58 }; 59 60 // Map of composite subreg indices. 61 typedef std::map<CodeGenSubRegIndex*, CodeGenSubRegIndex*, Less> CompMap; 62 63 // Returns the subreg index that results from composing this with Idx. 64 // Returns NULL if this and Idx don't compose. 65 CodeGenSubRegIndex *compose(CodeGenSubRegIndex *Idx) const { 66 CompMap::const_iterator I = Composed.find(Idx); 67 return I == Composed.end() ? 0 : I->second; 68 } 69 70 // Add a composite subreg index: this+A = B. 71 // Return a conflicting composite, or NULL 72 CodeGenSubRegIndex *addComposite(CodeGenSubRegIndex *A, 73 CodeGenSubRegIndex *B) { 74 assert(A && B); 75 std::pair<CompMap::iterator, bool> Ins = 76 Composed.insert(std::make_pair(A, B)); 77 return (Ins.second || Ins.first->second == B) ? 0 : Ins.first->second; 78 } 79 80 // Update the composite maps of components specified in 'ComposedOf'. 81 void updateComponents(CodeGenRegBank&); 82 83 // Clean out redundant composite mappings. 84 void cleanComposites(); 85 86 // Return the map of composites. 87 const CompMap &getComposites() const { return Composed; } 88 89 private: 90 CompMap Composed; 91 }; 92 93 /// CodeGenRegister - Represents a register definition. 94 struct CodeGenRegister { 95 Record *TheDef; 96 unsigned EnumValue; 97 unsigned CostPerUse; 98 bool CoveredBySubRegs; 99 100 // Map SubRegIndex -> Register. 101 typedef std::map<CodeGenSubRegIndex*, CodeGenRegister*, 102 CodeGenSubRegIndex::Less> SubRegMap; 103 104 CodeGenRegister(Record *R, unsigned Enum); 105 106 const std::string &getName() const; 107 108 // Extract more information from TheDef. This is used to build an object 109 // graph after all CodeGenRegister objects have been created. 110 void buildObjectGraph(CodeGenRegBank&); 111 112 // Lazily compute a map of all sub-registers. 113 // This includes unique entries for all sub-sub-registers. 114 const SubRegMap &computeSubRegs(CodeGenRegBank&); 115 116 // Compute extra sub-registers by combining the existing sub-registers. 117 void computeSecondarySubRegs(CodeGenRegBank&); 118 119 // Add this as a super-register to all sub-registers after the sub-register 120 // graph has been built. 121 void computeSuperRegs(CodeGenRegBank&); 122 123 const SubRegMap &getSubRegs() const { 124 assert(SubRegsComplete && "Must precompute sub-registers"); 125 return SubRegs; 126 } 127 128 // Add sub-registers to OSet following a pre-order defined by the .td file. 129 void addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet, 130 CodeGenRegBank&) const; 131 132 // Return the sub-register index naming Reg as a sub-register of this 133 // register. Returns NULL if Reg is not a sub-register. 134 CodeGenSubRegIndex *getSubRegIndex(const CodeGenRegister *Reg) const { 135 return SubReg2Idx.lookup(Reg); 136 } 137 138 typedef std::vector<const CodeGenRegister*> SuperRegList; 139 140 // Get the list of super-registers in topological order, small to large. 141 // This is valid after computeSubRegs visits all registers during RegBank 142 // construction. 143 const SuperRegList &getSuperRegs() const { 144 assert(SubRegsComplete && "Must precompute sub-registers"); 145 return SuperRegs; 146 } 147 148 // Get the list of ad hoc aliases. The graph is symmetric, so the list 149 // contains all registers in 'Aliases', and all registers that mention this 150 // register in 'Aliases'. 151 ArrayRef<CodeGenRegister*> getExplicitAliases() const { 152 return ExplicitAliases; 153 } 154 155 // Get the topological signature of this register. This is a small integer 156 // less than RegBank.getNumTopoSigs(). Registers with the same TopoSig have 157 // identical sub-register structure. That is, they support the same set of 158 // sub-register indices mapping to the same kind of sub-registers 159 // (TopoSig-wise). 160 unsigned getTopoSig() const { 161 assert(SuperRegsComplete && "TopoSigs haven't been computed yet."); 162 return TopoSig; 163 } 164 165 // List of register units in ascending order. 166 typedef SmallVector<unsigned, 16> RegUnitList; 167 168 // How many entries in RegUnitList are native? 169 unsigned NumNativeRegUnits; 170 171 // Get the list of register units. 172 // This is only valid after computeSubRegs() completes. 173 const RegUnitList &getRegUnits() const { return RegUnits; } 174 175 // Get the native register units. This is a prefix of getRegUnits(). 176 ArrayRef<unsigned> getNativeRegUnits() const { 177 return makeArrayRef(RegUnits).slice(0, NumNativeRegUnits); 178 } 179 180 // Inherit register units from subregisters. 181 // Return true if the RegUnits changed. 182 bool inheritRegUnits(CodeGenRegBank &RegBank); 183 184 // Adopt a register unit for pressure tracking. 185 // A unit is adopted iff its unit number is >= NumNativeRegUnits. 186 void adoptRegUnit(unsigned RUID) { RegUnits.push_back(RUID); } 187 188 // Get the sum of this register's register unit weights. 189 unsigned getWeight(const CodeGenRegBank &RegBank) const; 190 191 // Order CodeGenRegister pointers by EnumValue. 192 struct Less { 193 bool operator()(const CodeGenRegister *A, 194 const CodeGenRegister *B) const { 195 assert(A && B); 196 return A->EnumValue < B->EnumValue; 197 } 198 }; 199 200 // Canonically ordered set. 201 typedef std::set<const CodeGenRegister*, Less> Set; 202 203 // Compute the set of registers overlapping this. 204 void computeOverlaps(Set &Overlaps, const CodeGenRegBank&) const; 205 206 private: 207 bool SubRegsComplete; 208 bool SuperRegsComplete; 209 unsigned TopoSig; 210 211 // The sub-registers explicit in the .td file form a tree. 212 SmallVector<CodeGenSubRegIndex*, 8> ExplicitSubRegIndices; 213 SmallVector<CodeGenRegister*, 8> ExplicitSubRegs; 214 215 // Explicit ad hoc aliases, symmetrized to form an undirected graph. 216 SmallVector<CodeGenRegister*, 8> ExplicitAliases; 217 218 // Super-registers where this is the first explicit sub-register. 219 SuperRegList LeadingSuperRegs; 220 221 SubRegMap SubRegs; 222 SuperRegList SuperRegs; 223 DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*> SubReg2Idx; 224 RegUnitList RegUnits; 225 }; 226 227 228 class CodeGenRegisterClass { 229 CodeGenRegister::Set Members; 230 // Allocation orders. Order[0] always contains all registers in Members. 231 std::vector<SmallVector<Record*, 16> > Orders; 232 // Bit mask of sub-classes including this, indexed by their EnumValue. 233 BitVector SubClasses; 234 // List of super-classes, topologocally ordered to have the larger classes 235 // first. This is the same as sorting by EnumValue. 236 SmallVector<CodeGenRegisterClass*, 4> SuperClasses; 237 Record *TheDef; 238 std::string Name; 239 240 // For a synthesized class, inherit missing properties from the nearest 241 // super-class. 242 void inheritProperties(CodeGenRegBank&); 243 244 // Map SubRegIndex -> sub-class. This is the largest sub-class where all 245 // registers have a SubRegIndex sub-register. 246 DenseMap<CodeGenSubRegIndex*, CodeGenRegisterClass*> SubClassWithSubReg; 247 248 // Map SubRegIndex -> set of super-reg classes. This is all register 249 // classes SuperRC such that: 250 // 251 // R:SubRegIndex in this RC for all R in SuperRC. 252 // 253 DenseMap<CodeGenSubRegIndex*, 254 SmallPtrSet<CodeGenRegisterClass*, 8> > SuperRegClasses; 255 256 // Bit vector of TopoSigs for the registers in this class. This will be 257 // very sparse on regular architectures. 258 BitVector TopoSigs; 259 260 public: 261 unsigned EnumValue; 262 std::string Namespace; 263 std::vector<MVT::SimpleValueType> VTs; 264 unsigned SpillSize; 265 unsigned SpillAlignment; 266 int CopyCost; 267 bool Allocatable; 268 std::string AltOrderSelect; 269 270 // Return the Record that defined this class, or NULL if the class was 271 // created by TableGen. 272 Record *getDef() const { return TheDef; } 273 274 const std::string &getName() const { return Name; } 275 std::string getQualifiedName() const; 276 const std::vector<MVT::SimpleValueType> &getValueTypes() const {return VTs;} 277 unsigned getNumValueTypes() const { return VTs.size(); } 278 279 MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const { 280 if (VTNum < VTs.size()) 281 return VTs[VTNum]; 282 llvm_unreachable("VTNum greater than number of ValueTypes in RegClass!"); 283 } 284 285 // Return true if this this class contains the register. 286 bool contains(const CodeGenRegister*) const; 287 288 // Returns true if RC is a subclass. 289 // RC is a sub-class of this class if it is a valid replacement for any 290 // instruction operand where a register of this classis required. It must 291 // satisfy these conditions: 292 // 293 // 1. All RC registers are also in this. 294 // 2. The RC spill size must not be smaller than our spill size. 295 // 3. RC spill alignment must be compatible with ours. 296 // 297 bool hasSubClass(const CodeGenRegisterClass *RC) const { 298 return SubClasses.test(RC->EnumValue); 299 } 300 301 // getSubClassWithSubReg - Returns the largest sub-class where all 302 // registers have a SubIdx sub-register. 303 CodeGenRegisterClass* 304 getSubClassWithSubReg(CodeGenSubRegIndex *SubIdx) const { 305 return SubClassWithSubReg.lookup(SubIdx); 306 } 307 308 void setSubClassWithSubReg(CodeGenSubRegIndex *SubIdx, 309 CodeGenRegisterClass *SubRC) { 310 SubClassWithSubReg[SubIdx] = SubRC; 311 } 312 313 // getSuperRegClasses - Returns a bit vector of all register classes 314 // containing only SubIdx super-registers of this class. 315 void getSuperRegClasses(CodeGenSubRegIndex *SubIdx, BitVector &Out) const; 316 317 // addSuperRegClass - Add a class containing only SudIdx super-registers. 318 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, 319 CodeGenRegisterClass *SuperRC) { 320 SuperRegClasses[SubIdx].insert(SuperRC); 321 } 322 323 // getSubClasses - Returns a constant BitVector of subclasses indexed by 324 // EnumValue. 325 // The SubClasses vector includs an entry for this class. 326 const BitVector &getSubClasses() const { return SubClasses; } 327 328 // getSuperClasses - Returns a list of super classes ordered by EnumValue. 329 // The array does not include an entry for this class. 330 ArrayRef<CodeGenRegisterClass*> getSuperClasses() const { 331 return SuperClasses; 332 } 333 334 // Returns an ordered list of class members. 335 // The order of registers is the same as in the .td file. 336 // No = 0 is the default allocation order, No = 1 is the first alternative. 337 ArrayRef<Record*> getOrder(unsigned No = 0) const { 338 return Orders[No]; 339 } 340 341 // Return the total number of allocation orders available. 342 unsigned getNumOrders() const { return Orders.size(); } 343 344 // Get the set of registers. This set contains the same registers as 345 // getOrder(0). 346 const CodeGenRegister::Set &getMembers() const { return Members; } 347 348 // Get a bit vector of TopoSigs present in this register class. 349 const BitVector &getTopoSigs() const { return TopoSigs; } 350 351 // Populate a unique sorted list of units from a register set. 352 void buildRegUnitSet(std::vector<unsigned> &RegUnits) const; 353 354 CodeGenRegisterClass(CodeGenRegBank&, Record *R); 355 356 // A key representing the parts of a register class used for forming 357 // sub-classes. Note the ordering provided by this key is not the same as 358 // the topological order used for the EnumValues. 359 struct Key { 360 const CodeGenRegister::Set *Members; 361 unsigned SpillSize; 362 unsigned SpillAlignment; 363 364 Key(const Key &O) 365 : Members(O.Members), 366 SpillSize(O.SpillSize), 367 SpillAlignment(O.SpillAlignment) {} 368 369 Key(const CodeGenRegister::Set *M, unsigned S = 0, unsigned A = 0) 370 : Members(M), SpillSize(S), SpillAlignment(A) {} 371 372 Key(const CodeGenRegisterClass &RC) 373 : Members(&RC.getMembers()), 374 SpillSize(RC.SpillSize), 375 SpillAlignment(RC.SpillAlignment) {} 376 377 // Lexicographical order of (Members, SpillSize, SpillAlignment). 378 bool operator<(const Key&) const; 379 }; 380 381 // Create a non-user defined register class. 382 CodeGenRegisterClass(CodeGenRegBank&, StringRef Name, Key Props); 383 384 // Called by CodeGenRegBank::CodeGenRegBank(). 385 static void computeSubClasses(CodeGenRegBank&); 386 }; 387 388 // Register units are used to model interference and register pressure. 389 // Every register is assigned one or more register units such that two 390 // registers overlap if and only if they have a register unit in common. 391 // 392 // Normally, one register unit is created per leaf register. Non-leaf 393 // registers inherit the units of their sub-registers. 394 struct RegUnit { 395 // Weight assigned to this RegUnit for estimating register pressure. 396 // This is useful when equalizing weights in register classes with mixed 397 // register topologies. 398 unsigned Weight; 399 400 // Each native RegUnit corresponds to one or two root registers. The full 401 // set of registers containing this unit can be computed as the union of 402 // these two registers and their super-registers. 403 const CodeGenRegister *Roots[2]; 404 405 RegUnit() : Weight(0) { Roots[0] = Roots[1] = 0; } 406 407 ArrayRef<const CodeGenRegister*> getRoots() const { 408 assert(!(Roots[1] && !Roots[0]) && "Invalid roots array"); 409 return makeArrayRef(Roots, !!Roots[0] + !!Roots[1]); 410 } 411 }; 412 413 // Each RegUnitSet is a sorted vector with a name. 414 struct RegUnitSet { 415 typedef std::vector<unsigned>::const_iterator iterator; 416 417 std::string Name; 418 std::vector<unsigned> Units; 419 }; 420 421 // Base vector for identifying TopoSigs. The contents uniquely identify a 422 // TopoSig, only computeSuperRegs needs to know how. 423 typedef SmallVector<unsigned, 16> TopoSigId; 424 425 // CodeGenRegBank - Represent a target's registers and the relations between 426 // them. 427 class CodeGenRegBank { 428 SetTheory Sets; 429 430 // SubRegIndices. 431 std::vector<CodeGenSubRegIndex*> SubRegIndices; 432 DenseMap<Record*, CodeGenSubRegIndex*> Def2SubRegIdx; 433 434 CodeGenSubRegIndex *createSubRegIndex(StringRef Name, StringRef NameSpace); 435 436 typedef std::map<SmallVector<CodeGenSubRegIndex*, 8>, 437 CodeGenSubRegIndex*> ConcatIdxMap; 438 ConcatIdxMap ConcatIdx; 439 440 // Registers. 441 std::vector<CodeGenRegister*> Registers; 442 DenseMap<Record*, CodeGenRegister*> Def2Reg; 443 unsigned NumNativeRegUnits; 444 445 std::map<TopoSigId, unsigned> TopoSigs; 446 447 // Includes native (0..NumNativeRegUnits-1) and adopted register units. 448 SmallVector<RegUnit, 8> RegUnits; 449 450 // Register classes. 451 std::vector<CodeGenRegisterClass*> RegClasses; 452 DenseMap<Record*, CodeGenRegisterClass*> Def2RC; 453 typedef std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass*> RCKeyMap; 454 RCKeyMap Key2RC; 455 456 // Remember each unique set of register units. Initially, this contains a 457 // unique set for each register class. Simliar sets are coalesced with 458 // pruneUnitSets and new supersets are inferred during computeRegUnitSets. 459 std::vector<RegUnitSet> RegUnitSets; 460 461 // Map RegisterClass index to the index of the RegUnitSet that contains the 462 // class's units and any inferred RegUnit supersets. 463 std::vector<std::vector<unsigned> > RegClassUnitSets; 464 465 // Add RC to *2RC maps. 466 void addToMaps(CodeGenRegisterClass*); 467 468 // Create a synthetic sub-class if it is missing. 469 CodeGenRegisterClass *getOrCreateSubClass(const CodeGenRegisterClass *RC, 470 const CodeGenRegister::Set *Membs, 471 StringRef Name); 472 473 // Infer missing register classes. 474 void computeInferredRegisterClasses(); 475 void inferCommonSubClass(CodeGenRegisterClass *RC); 476 void inferSubClassWithSubReg(CodeGenRegisterClass *RC); 477 void inferMatchingSuperRegClass(CodeGenRegisterClass *RC, 478 unsigned FirstSubRegRC = 0); 479 480 // Iteratively prune unit sets. 481 void pruneUnitSets(); 482 483 // Compute a weight for each register unit created during getSubRegs. 484 void computeRegUnitWeights(); 485 486 // Create a RegUnitSet for each RegClass and infer superclasses. 487 void computeRegUnitSets(); 488 489 // Populate the Composite map from sub-register relationships. 490 void computeComposites(); 491 492 public: 493 CodeGenRegBank(RecordKeeper&); 494 495 SetTheory &getSets() { return Sets; } 496 497 // Sub-register indices. The first NumNamedIndices are defined by the user 498 // in the .td files. The rest are synthesized such that all sub-registers 499 // have a unique name. 500 ArrayRef<CodeGenSubRegIndex*> getSubRegIndices() { return SubRegIndices; } 501 502 // Find a SubRegIndex form its Record def. 503 CodeGenSubRegIndex *getSubRegIdx(Record*); 504 505 // Find or create a sub-register index representing the A+B composition. 506 CodeGenSubRegIndex *getCompositeSubRegIndex(CodeGenSubRegIndex *A, 507 CodeGenSubRegIndex *B); 508 509 // Find or create a sub-register index representing the concatenation of 510 // non-overlapping sibling indices. 511 CodeGenSubRegIndex * 512 getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex*, 8>&); 513 514 void 515 addConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex*, 8> &Parts, 516 CodeGenSubRegIndex *Idx) { 517 ConcatIdx.insert(std::make_pair(Parts, Idx)); 518 } 519 520 const std::vector<CodeGenRegister*> &getRegisters() { return Registers; } 521 522 // Find a register from its Record def. 523 CodeGenRegister *getReg(Record*); 524 525 // Get a Register's index into the Registers array. 526 unsigned getRegIndex(const CodeGenRegister *Reg) const { 527 return Reg->EnumValue - 1; 528 } 529 530 // Return the number of allocated TopoSigs. The first TopoSig representing 531 // leaf registers is allocated number 0. 532 unsigned getNumTopoSigs() const { 533 return TopoSigs.size(); 534 } 535 536 // Find or create a TopoSig for the given TopoSigId. 537 // This function is only for use by CodeGenRegister::computeSuperRegs(). 538 // Others should simply use Reg->getTopoSig(). 539 unsigned getTopoSig(const TopoSigId &Id) { 540 return TopoSigs.insert(std::make_pair(Id, TopoSigs.size())).first->second; 541 } 542 543 // Create a native register unit that is associated with one or two root 544 // registers. 545 unsigned newRegUnit(CodeGenRegister *R0, CodeGenRegister *R1 = 0) { 546 RegUnits.resize(RegUnits.size() + 1); 547 RegUnits.back().Roots[0] = R0; 548 RegUnits.back().Roots[1] = R1; 549 return RegUnits.size() - 1; 550 } 551 552 // Create a new non-native register unit that can be adopted by a register 553 // to increase its pressure. Note that NumNativeRegUnits is not increased. 554 unsigned newRegUnit(unsigned Weight) { 555 RegUnits.resize(RegUnits.size() + 1); 556 RegUnits.back().Weight = Weight; 557 return RegUnits.size() - 1; 558 } 559 560 // Native units are the singular unit of a leaf register. Register aliasing 561 // is completely characterized by native units. Adopted units exist to give 562 // register additional weight but don't affect aliasing. 563 bool isNativeUnit(unsigned RUID) { 564 return RUID < NumNativeRegUnits; 565 } 566 567 unsigned getNumNativeRegUnits() const { 568 return NumNativeRegUnits; 569 } 570 571 RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; } 572 const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; } 573 574 ArrayRef<CodeGenRegisterClass*> getRegClasses() const { 575 return RegClasses; 576 } 577 578 // Find a register class from its def. 579 CodeGenRegisterClass *getRegClass(Record*); 580 581 /// getRegisterClassForRegister - Find the register class that contains the 582 /// specified physical register. If the register is not in a register 583 /// class, return null. If the register is in multiple classes, and the 584 /// classes have a superset-subset relationship and the same set of types, 585 /// return the superclass. Otherwise return null. 586 const CodeGenRegisterClass* getRegClassForRegister(Record *R); 587 588 // Get the sum of unit weights. 589 unsigned getRegUnitSetWeight(const std::vector<unsigned> &Units) const { 590 unsigned Weight = 0; 591 for (std::vector<unsigned>::const_iterator 592 I = Units.begin(), E = Units.end(); I != E; ++I) 593 Weight += getRegUnit(*I).Weight; 594 return Weight; 595 } 596 597 // Increase a RegUnitWeight. 598 void increaseRegUnitWeight(unsigned RUID, unsigned Inc) { 599 getRegUnit(RUID).Weight += Inc; 600 } 601 602 // Get the number of register pressure dimensions. 603 unsigned getNumRegPressureSets() const { return RegUnitSets.size(); } 604 605 // Get a set of register unit IDs for a given dimension of pressure. 606 RegUnitSet getRegPressureSet(unsigned Idx) const { 607 return RegUnitSets[Idx]; 608 } 609 610 // Get a list of pressure set IDs for a register class. Liveness of a 611 // register in this class impacts each pressure set in this list by the 612 // weight of the register. An exact solution requires all registers in a 613 // class to have the same class, but it is not strictly guaranteed. 614 ArrayRef<unsigned> getRCPressureSetIDs(unsigned RCIdx) const { 615 return RegClassUnitSets[RCIdx]; 616 } 617 618 // Computed derived records such as missing sub-register indices. 619 void computeDerivedInfo(); 620 621 // Compute the set of registers completely covered by the registers in Regs. 622 // The returned BitVector will have a bit set for each register in Regs, 623 // all sub-registers, and all super-registers that are covered by the 624 // registers in Regs. 625 // 626 // This is used to compute the mask of call-preserved registers from a list 627 // of callee-saves. 628 BitVector computeCoveredRegisters(ArrayRef<Record*> Regs); 629 }; 630 } 631 632 #endif 633