| /external/llvm/utils/TableGen/ |
| AsmWriterInst.cpp | 127 CGI.TheDef->getName() + "'!";
166 + CGI.TheDef->getName() + "'";
173 + CGI.TheDef->getName() + "'";
181 throw "Bad operand modifier name in '"+ CGI.TheDef->getName() + "'";
186 + CGI.TheDef->getName() + "'";
190 throw "Stray '$' in '" + CGI.TheDef->getName() +
|
| CodeGenIntrinsics.h | 27 Record *TheDef; // The actual record defining this intrinsic.
|
| InstrInfoEmitter.cpp | 204 Record *Inst = (*II)->TheDef;
237 InstrNames.add(Instr->TheDef->getName());
250 OS << InstrNames.get(Instr->TheDef->getName()) << "U, ";
307 Record *ItinDef = Inst.TheDef->getValueAsDef("Itinerary");
312 << Inst.TheDef->getValueAsInt("Size") << ",\t0";
345 BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
352 throw "Invalid TSFlags bit in " + Inst.TheDef->getName();
359 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
365 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
378 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n"
[all...] |
| AsmMatcherEmitter.cpp | 384 /// TheDef - This is the definition of the instruction or InstAlias that this
386 Record *const TheDef;
424 : AsmVariantID(0), TheDef(CGI.TheDef), DefRec(&CGI),
429 : AsmVariantID(0), TheDef(Alias->TheDef), DefRec(Alias),
552 Record *TheDef;
557 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
561 return "Feature_" + TheDef->getName();
668 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n"
[all...] |
| CodeGenInstruction.cpp | 28 CGIOperandList::CGIOperandList(Record *R) : TheDef(R) {
137 throw "'" + TheDef->getName() + "' does not have an operand named '$" +
157 throw TheDef->getName() + ": Illegal operand name: '" + Op + "'";
167 throw TheDef->getName() + ": illegal empty suboperand name in '" +Op +"'";
177 throw TheDef->getName() + ": Illegal to refer to"
187 throw TheDef->getName() + ": unknown suboperand name in '" + Op + "'";
195 throw TheDef->getName() + ": unknown suboperand name in '" + Op + "'";
291 : TheDef(R), Operands(R), InferredFrom(0) {
516 CodeGenInstAlias::CodeGenInstAlias(Record *R, CodeGenTarget &T) : TheDef(R) {
|
| CodeGenRegisters.cpp | 31 : TheDef(R), EnumValue(Enum) {
39 : TheDef(0), Name(N), Namespace(Nspace), EnumValue(Enum) {
51 if (!TheDef)
54 std::vector<Record*> Comps = TheDef->getValueAsListOfDefs("ComposedOf");
57 throw TGError(TheDef->getLoc(), "ComposedOf must have exactly two entries");
62 throw TGError(TheDef->getLoc(), "Ambiguous ComposedOf entries");
66 TheDef->getValueAsListOfDefs("CoveringSubRegIndices");
69 throw TGError(TheDef->getLoc(),
93 : TheDef(R),
104 std::vector<Record*> SRIs = TheDef->getValueAsListOfDefs("SubRegIndices")
[all...] |
| AsmWriterEmitter.cpp | 104 << FirstInst.CGI->TheDef->getName() << ":\n";
107 << SimilarInsts[i].CGI->TheDef->getName() << ":\n";
118 FirstInst.CGI->TheDef->getName(),
124 AWI.CGI->TheDef->getName(),
167 InstrsForCase[idx] += Inst->CGI->TheDef->getName();
174 InstrsForCase.push_back(Inst->CGI->TheDef->getName());
295 (*I)->TheDef->getName() != "PHI")
417 << NumberedInstructions[i]->TheDef->getName() << "\n";
522 AsmName = Reg.TheDef->getValueAsString("AsmName");
528 Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices")
[all...] |
| CodeGenInstruction.h | 128 Record *TheDef; // The actual record containing this OperandList.
203 Record *TheDef; // The actual record defining this instruction.
280 Record *TheDef; // The actual record defining this InstAlias.
|
| CodeGenRegisters.h | 37 Record *const TheDef;
95 Record *TheDef;
108 // Extract more information from TheDef. This is used to build an object
237 Record *TheDef;
272 Record *getDef() const { return TheDef; }
|
| RegisterInfoEmitter.cpp | 76 std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
256 Record *Reg = Regs[i]->TheDef;
274 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
323 Record *Reg = Regs[i]->TheDef;
379 Record *Reg = Regs[i]->TheDef;
387 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
672 OS << " { " << getQualifiedName(Roots.front()->TheDef);
674 OS << ", " << getQualifiedName(Roots[r]->TheDef);
750 Record *Reg = Regs[i]->TheDef;
[all...] |
| FixedLenDecoderEmitter.cpp | 375 BitsInit &Bits = getBitsField(*AllInstructions[Opcode]->TheDef, "Inst");
383 AllInstructions[Opcode]->TheDef->getValueAsBitsInit("SoftFail");
395 return AllInstructions[Opcode]->TheDef->getName();
831 << NumberedInstructions->at(Opc)->TheDef->getName() << "\n";
[all...] |
| EDEmitter.cpp | 366 if (!inst.TheDef->isSubClassOf("X86Inst"))
380 errs() << "Instruction name: " << inst.TheDef->getName().c_str() << "\n";
448 const std::string &name = inst.TheDef->getName();
758 if (!inst.TheDef->isSubClassOf("InstARM") &&
759 !inst.TheDef->isSubClassOf("InstThumb"))
778 errs() << "Instruction name: " << inst.TheDef->getName() << '\n';
802 const std::string &name = inst.TheDef->getName();
[all...] |
| CodeGenDAGPatterns.h | 724 if (Intrinsics[i].TheDef == R) return Intrinsics[i];
726 if (TgtIntrinsics[i].TheDef == R) return TgtIntrinsics[i];
740 if (Intrinsics[i].TheDef == R) return i;
742 if (TgtIntrinsics[i].TheDef == R) return i + Intrinsics.size();
|
| CodeGenSchedule.cpp | 49 Record *SchedDef = (*I)->TheDef->getValueAsDef("Itinerary");
|
| CodeGenTarget.cpp | 204 if (Regs[i]->TheDef->getValueAsString("AsmName") == Name)
278 return Rec1->TheDef->getName() < Rec2->TheDef->getName();
405 TheDef = R;
|
| PseudoLoweringEmitter.cpp | 211 << Source.TheDef->getName() << ": {\n"
215 << Dest.TheDef->getName() << ");\n";
|
| CodeEmitterGen.cpp | 259 Record *R = CGI->TheDef;
|
| DAGISelMatcherEmitter.cpp | 443 OS << "TARGET_VAL(" << getQualifiedName(Reg->TheDef) << "),\n";
448 OS << getQualifiedName(Reg->TheDef) << ",\n";
|
| X86RecognizableInstr.cpp | 213 Rec = insn.TheDef;
284 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
[all...] |
| IntrinsicEmitter.cpp | 703 throw "Intrinsic '" + Ints[i].TheDef->getName() +
|
| CodeGenDAGPatterns.cpp | [all...] |
| DAGISelMatcherGen.cpp | [all...] |
