| /external/llvm/test/MC/MachO/ |
| relax-jumps.s | 21 jb L2
23 jg L2
25 jae L2
29 L2:
|
| relax-recompute-align.s | 29 jle L2
35 L2:
|
| darwin-x86_64-diff-relocs.s | 45 jmp L2
50 // jmp L2 - _g3
74 movl %eax,L2(%rip)
81 // movl %eax,L2 - _g2(%rip)
94 L2:
98 .quad L2
101 .quad L2 - _g2
|
| /external/clang/include/clang/Basic/ |
| Linkage.h | 63 inline Linkage minLinkage(Linkage L1, Linkage L2) {
64 return L1 < L2? L1 : L2;
|
| /external/clang/test/CodeGen/ |
| indirect-goto.c | 4 void *addrs[] = { &&L1, &&L2, &&L3, &&L4, &&L5 };
11 L2: res *= 3;
17 static const void *addrs[] = { &&L1, &&L2, &&L3, &&L4, &&L5 };
24 L2: res *= 3;
|
| /external/clang/test/CodeGenCXX/ |
| mangle-local-classes-nested.cpp | 17 void L2() {
32 S().L2();
36 void L2() {
51 S().L2();
|
| /bionic/libc/arch-x86/string/ |
| strcpy.S | 31 jz L2
35 jz L2
39 jz L2
43 jz L2
47 jz L2
51 jz L2
55 jz L2
62 L2: popl %eax /* pop dst address */
|
| index.S | 20 je L2
25 L2:
|
| strcat.S | 40 jz L2
44 jz L2
48 jz L2
52 jz L2
56 jz L2
60 jz L2
64 jz L2
71 L2: popl %eax /* pop destination address */
|
| bcmp.S | 27 je L2
30 L2: popl %esi
|
| rindex.S | 22 jne L2
24 L2:
|
| swab.S | 26 jz L2 # while swaping alternate bytes.
35 L2: shrl $3,%ecx # copy remainder 8 words at a time
|
| /external/clang/test/Sema/ |
| scope-check.c | 61 goto L2; // expected-error {{goto into protected scope}}
64 L2:;
138 L2: ;
148 &&L2,
161 goto L2; // expected-error {{goto into protected scope}}
163 L2:
186 goto L2;
187 L2:
221 static const void *addrs[] = { &&L1, &&L2 };
228 L2: // expected-note {{possible target}
[all...] |
| warn-duplicate-enum.c | 76 L2 = L1,
77 L3 = L2
|
| /external/clang/test/SemaCXX/ |
| return-noreturn.cpp | 34 switch (x) default: L1: L2: case 4: pr6884_abort_struct();
37 switch (x) default: L1: { L2: case 4: pr6884_abort_struct(); }
40 switch (x) default: L1: L2: case 4: { pr6884_abort_struct(); }
63 switch (x) default: L1: L2: case 4: pr6884_abort_struct();
67 switch (x) default: L1: { L2: case 4: pr6884_abort_struct(); }
71 switch (x) default: L1: L2: case 4: { pr6884_abort_struct(); }
90 switch (x) default: L1: L2: case 4: pr6884_abort_struct a;
94 switch (x) default: L1: { L2: case 4: pr6884_abort_struct a; }
98 switch (x) default: L1: L2: case 4: { pr6884_abort_struct a; }
|
| warn-unique-enum.cpp | 26 L1 = 0x8000000000000000ULL, L2 = 0x0000000000000001ULL
|
| /external/oprofile/events/i386/westmere/ |
| unit_masks | 58 0x01 l1d_l2 Cycles L1D and L2 locked
119 0x01 i_state L1 writebacks to L2 in I state (misses)
120 0x02 s_state L1 writebacks to L2 in S state
121 0x04 e_state L1 writebacks to L2 in E state
122 0x08 m_state L1 writebacks to L2 in M state
123 0x0f mesi All L1 writebacks to L2
130 0x01 demand_i_state L2 data demand loads in I state (misses)
131 0x02 demand_s_state L2 data demand loads in S state
132 0x04 demand_e_state L2 data demand loads in E state
133 0x08 demand_m_state L2 data demand loads in M stat
[all...] |
| /frameworks/base/tests/RenderScriptTests/tests/src/com/android/rs/test/ |
| UT_vector.java | 221 Long2 L2 = s.get_u32_2();
222 if (L2.x != 1 || L2.y != 2) {
225 L2.x = 2;
226 L2.y = 3;
227 s.set_u32_2(L2);
248 L2 = s.get_i64_2();
249 if (L2.x != 1 || L2.y != 2) {
252 L2.x = 2
[all...] |
| /frameworks/base/tests/RenderScriptTests/tests_v14/src/com/android/rs/test/ |
| UT_vector.java | 221 Long2 L2 = s.get_u32_2();
222 if (L2.x != 1 || L2.y != 2) {
225 L2.x = 2;
226 L2.y = 3;
227 s.set_u32_2(L2);
248 L2 = s.get_i64_2();
249 if (L2.x != 1 || L2.y != 2) {
252 L2.x = 2
[all...] |
| /external/llvm/test/MC/MachO/ARM/ |
| thumb2-movw-fixup.s | 12 movw r12, :lower16:L2
13 movt r12, :upper16:L2
18 L2: .long 0
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/reference/vc/m4p10/src/ |
| omxVCM4P10_PredictIntra_4x4.c | 142 * L2 xx xx xx xx
157 #define L2 pSrcLeft[2*leftStep]
177 pDst[2*dstStep+x] = L2;
217 pTmp[0] = (OMX_U8)((L1 + 2*L2 + L3 + 2)>>2);
218 pTmp[1] = (OMX_U8)((L0 + 2*L1 + L2 + 2)>>2);
238 pTmp[0] = (OMX_U8)((L2 + 2*L1 + L0 + 2)>>2);
268 pTmp[6] = (OMX_U8)((L0 + 2*L1 + L2 + 2)>>2);
269 pTmp[7] = (OMX_U8)((L1 + L2 + 1)>>1);
270 pTmp[8] = (OMX_U8)((L1 + 2*L2 + L3 + 2)>>2);
271 pTmp[9] = (OMX_U8)((L2 + L3 + 1)>>1)
[all...] |
| /frameworks/ml/bordeaux/learning/stochastic_linear_ranker/native/ |
| common_defs.h | 25 enum RegularizationType { L0, L1, L2, L1L2, L1LInf };
|
| /external/oprofile/events/i386/nehalem/ |
| unit_masks | 46 0x08 remote_cache_local_home_hit Counts number of memory load instructions retired where the memory reference missed the L1, L2 and LLC caches and HIT in a remote socket's cache
47 0x10 remote_dram Counts number of memory load instructions retired where the memory reference missed the L1, L2 and LLC caches and was remotely homed
48 0x20 local_dram Counts number of memory load instructions retired where the memory reference missed the L1, L2 and LLC caches and required a local socket memory reference
81 0x01 ld_hit Counts number of loads that hit the L2 cache
82 0x02 ld_miss Counts the number of loads that miss the L2 cache
83 0x03 loads Counts all L2 load requests
84 0x04 rfo_hit Counts the number of store RFO requests that hit the L2 cache
85 0x08 rfo_miss Counts the number of store RFO requests that miss the L2 cache
86 0x0C rfos Counts all L2 store RFO requests
87 0x10 ifetch_hit Counts number of instruction fetches that hit the L2 cach
[all...] |
| /external/oprofile/events/i386/atom/ |
| events | 23 event:0x21 counters:0,1 um:core minimum:6000 name:CORE : Cycles L2 address bus is in use
24 event:0x22 counters:0,1 um:core minimum:6000 name:L2_DBUS_BUSY : Cycles the L2 cache data bus is busy
25 event:0x24 counters:0,1 um:core,prefetch minimum:500 name:L2_LINES_IN : L2 cache misses
26 event:0x25 counters:0,1 um:core minimum:500 name:L2_M_LINES_IN : L2 cache line modifications
27 event:0x26 counters:0,1 um:core,prefetch minimum:500 name:L2_LINES_OUT : L2 cache lines evicted
28 event:0x27 counters:0,1 um:core,prefetch minimum:500 name:L2_M_LINES_OUT : Modified lines evicted from the L2 cache
29 event:0x28 counters:0,1 um:core,mesi minimum:6000 name:L2_IFETCH : L2 cacheable instruction fetch requests
30 event:0x29 counters:0,1 um:core,prefetch,mesi minimum:6000 name:L2_LD : L2 cache reads
31 event:0x2A counters:0,1 um:core,mesi minimum:6000 name:L2_ST : L2 store requests
32 event:0x2B counters:0,1 um:core,mesi minimum:6000 name:L2_LOCK : L2 locked accesse
[all...] |
| /external/clang/test/FixIt/ |
| fixit.c | 71 /*preserved comment*/ L2 : c++; // expected-warning {{unused label}}
|
