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    Searched refs:MinLatency (Results 1 - 7 of 7) sorted by null

  /external/llvm/include/llvm/MC/
MCSchedule.h 43 // MinLatency is the minimum latency between a register write
48 // hazard. MinLatency can always be overridden by the number of
52 // Use InstrItinerary OperandCycles as MinLatency.
63 int MinLatency;
68 // If MinLatency >= 0, this may be overriden for individual load opcodes by
77 // If MinLatency >= 0, this may be overriden by InstrItinData OperandCycles.
99 MinLatency(DefaultMinLatency),
108 IssueWidth(iw), MinLatency(ml), LoadLatency(ll), HighLatency(hl),
MCInstrItineraries.h 160 /// InstrStages override the itinerary's MinLatency property. In fact, if the
161 /// stage latencies, which may be zero, are less than MinLatency,
162 /// getStageLatency returns a value less than MinLatency.
164 /// If no stages exist, MinLatency is used. If MinLatency is invalid (<0),
170 return SchedModel->MinLatency < 0 ? 1 : SchedModel->MinLatency;
  /external/llvm/include/llvm/CodeGen/
ScheduleDAG.h 88 /// Record MinLatency seperately from "expected" Latency.
89 unsigned MinLatency;
101 : Dep(S, kind), Contents(), Latency(latency), MinLatency(latency) {
141 && Latency == Other.Latency && MinLatency == Other.MinLatency;
165 return MinLatency;
170 MinLatency = Lat;
  /external/llvm/lib/Target/Hexagon/
HexagonMachineScheduler.cpp 63 /// FIXME: Adjust SuccSU height based on MinLatency.
91 /// FIXME: Adjust PredSU height based on MinLatency.
487 unsigned MinLatency = I->getMinLatency();
489 Top.MaxMinLatency = std::max(MinLatency, Top.MaxMinLatency);
491 if (SU->TopReadyCycle < PredReadyCycle + MinLatency)
492 SU->TopReadyCycle = PredReadyCycle + MinLatency;
506 unsigned MinLatency = I->getMinLatency();
508 Bot.MaxMinLatency = std::max(MinLatency, Bot.MaxMinLatency);
510 if (SU->BotReadyCycle < SuccReadyCycle + MinLatency)
511 SU->BotReadyCycle = SuccReadyCycle + MinLatency;
    [all...]
  /external/llvm/lib/CodeGen/
MachineScheduler.cpp 438 /// FIXME: Adjust SuccSU height based on MinLatency.
466 /// FIXME: Adjust PredSU height based on MinLatency.
910 unsigned MinLatency = I->getMinLatency();
912 Top.MaxMinLatency = std::max(MinLatency, Top.MaxMinLatency);
914 if (SU->TopReadyCycle < PredReadyCycle + MinLatency)
915 SU->TopReadyCycle = PredReadyCycle + MinLatency;
929 unsigned MinLatency = I->getMinLatency();
931 Bot.MaxMinLatency = std::max(MinLatency, Bot.MaxMinLatency);
933 if (SU->BotReadyCycle < SuccReadyCycle + MinLatency)
934 SU->BotReadyCycle = SuccReadyCycle + MinLatency;
    [all...]
ScheduleDAGInstrs.cpp 281 unsigned MinLatency =
285 dep.setMinLatency(MinLatency);
483 unsigned MinLatency =
486 dep.setMinLatency(MinLatency);
    [all...]
TargetInstrInfoImpl.cpp 578 // still have a MinLatency property, which getStageLatency checks.
621 // If MinLatency is valid, call getInstrLatency. This uses Stage latency if
622 // it exists before defaulting to MinLatency.
623 if (ItinData->SchedModel->MinLatency >= 0)
626 // If MinLatency is invalid, OperandLatency is interpreted as MinLatency.

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