| /external/llvm/include/llvm/ |
| Constant.h | 47 Constant(Type *ty, ValueTy vty, Use *Ops, unsigned NumOps)
48 : User(ty, vty, Ops, NumOps) {}
|
| InlineAsm.h | 232 static unsigned getFlagWord(unsigned Kind, unsigned NumOps) {
233 assert(((NumOps << 3) & ~0xffff) == 0 && "Too many inline asm operands!");
235 return Kind | (NumOps << 3);
|
| User.h | 52 User(Type *ty, unsigned vty, Use *OpList, unsigned NumOps)
53 : Value(ty, vty), OperandList(OpList), NumOperands(NumOps) {}
|
| GlobalValue.h | 59 GlobalValue(Type *ty, ValueTy vty, Use *Ops, unsigned NumOps,
61 : Constant(ty, vty, Ops, NumOps), Linkage(linkage),
|
| Instruction.h | 386 Instruction(Type *Ty, unsigned iType, Use *Ops, unsigned NumOps,
388 Instruction(Type *Ty, unsigned iType, Use *Ops, unsigned NumOps,
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| InstrTypes.h | 38 Use *Ops, unsigned NumOps,
40 : Instruction(Ty, iType, Ops, NumOps, InsertBefore) {}
43 Use *Ops, unsigned NumOps, BasicBlock *InsertAtEnd)
44 : Instruction(Ty, iType, Ops, NumOps, InsertAtEnd) {}
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAG.h | 563 const SDUse *Ops, unsigned NumOps);
565 const SDValue *Ops, unsigned NumOps);
568 const SDValue *Ops, unsigned NumOps);
570 const SDValue *Ops, unsigned NumOps);
572 const SDValue *Ops, unsigned NumOps);
673 const SDValue *Ops, unsigned NumOps,
679 const SDValue *Ops, unsigned NumOps,
685 const SDValue *Ops, unsigned NumOps,
689 SDValue getMergeValues(const SDValue *Ops, unsigned NumOps, DebugLoc dl);
[all...] |
| SelectionDAGISel.h | 247 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo);
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| SelectionDAGNodes.h | 683 unsigned NumOps)
686 OperandList(NumOps ? new SDUse[NumOps] : 0),
688 NumOperands(NumOps), NumValues(VTs.NumVTs),
690 for (unsigned i = 0; i != NumOps; ++i) {
906 unsigned NumOps, EVT MemoryVT, MachineMemOperand *MMO);
[all...] |
| /external/llvm/lib/CodeGen/ |
| CallingConvLower.cpp | 120 unsigned NumOps = Outs.size();
121 for (unsigned i = 0; i != NumOps; ++i) {
139 unsigned NumOps = ArgVTs.size();
140 for (unsigned i = 0; i != NumOps; ++i) {
|
| MachineInstr.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.cpp | 136 unsigned NumOps = Outs.size();
146 for (; i != NumOps; ++i) {
164 unsigned NumOps = ArgVTs.size();
165 for (unsigned i = 0; i != NumOps; ++i) {
|
| /external/llvm/lib/Target/X86/ |
| X86CodeEmitter.cpp | 169 unsigned NumOps = Desc.getNumOperands();
170 if (NumOps) {
171 bool isTwoAddr = NumOps > 1 &&
176 for (unsigned e = NumOps; i != e; ++i) {
194 for (unsigned e = NumOps; i != e; ++i) {
206 for (; i != NumOps; ++i) {
223 if (NumOps > e && X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e)))
240 for (unsigned e = NumOps; i != e; ++i) {
[all...] |
| X86FloatingPoint.cpp | [all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 573 unsigned NumOps = Desc.getNumOperands();
575 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0)
577 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0) {
578 assert(Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1);
735 unsigned NumOps = MI.getNumOperands();
737 bool isTwoAddr = NumOps > 1 &&
742 for (; i != NumOps; ++i) {
760 for (; i != NumOps; ++i) {
772 for (; i != NumOps; ++i) {
789 if (NumOps > e && MI.getOperand(e).isReg() &
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAG.cpp | 356 const SDValue *Ops, unsigned NumOps) {
357 for (; NumOps; --NumOps, ++Ops) {
366 const SDUse *Ops, unsigned NumOps) {
367 for (; NumOps; --NumOps, ++Ops) {
789 const SDValue *Ops,unsigned NumOps,
795 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, NumOps);
[all...] |
| LegalizeTypes.cpp | 415 for (unsigned i = 0, NumOps = I->getNumOperands(); i < NumOps; ++i)
[all...] |
| ScheduleDAGFast.cpp | 477 unsigned NumOps = Node->getNumOperands();
478 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
479 --NumOps; // Ignore the glue operand.
481 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
|
| InstrEmitter.cpp | 602 unsigned NumOps = Node->getNumOperands();
603 assert((NumOps & 1) == 1 &&
606 for (unsigned i = 1; i != NumOps; ++i) {
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 658 unsigned NumOps = MCID.getNumOperands();
659 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
660 if (HasCC && MI->getOperand(NumOps-1).isDead())
684 unsigned NumOps = MCID.getNumOperands();
686 if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
749 unsigned NumOps = MCID.getNumOperands();
750 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
751 if (HasCC && MI->getOperand(NumOps-1).isDead())
775 unsigned NumOps = MCID.getNumOperands();
777 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()
[all...] |
| /external/llvm/lib/VMCore/ |
| Instruction.cpp | 23 Instruction::Instruction(Type *ty, unsigned it, Use *Ops, unsigned NumOps,
25 : User(ty, Value::InstructionVal + it, Ops, NumOps), Parent(0) {
37 Instruction::Instruction(Type *ty, unsigned it, Use *Ops, unsigned NumOps,
39 : User(ty, Value::InstructionVal + it, Ops, NumOps), Parent(0) {
|
| Instructions.cpp | 143 unsigned NumOps = e + e / 2;
144 if (NumOps < 2) NumOps = 2; // 2 op PHI nodes are VERY common.
149 ReservedSpace = NumOps;
[all...] |
| /external/llvm/utils/TableGen/ |
| AsmWriterEmitter.cpp | 400 unsigned NumOps = NumInstOpsHandled[InstIdxs[i]];
401 assert(NumOps <= Inst->Operands.size() &&
404 Inst->Operands.begin()+NumOps);
709 unsigned NumOps = 0;
713 ++NumOps;
717 return NumOps;
721 unsigned NumOps = 0;
733 ++NumOps;
738 return NumOps;
[all...] |
| CodeGenInstruction.cpp | 71 unsigned NumOps = 1;
92 NumOps = NumArgs;
117 OperandType, MIOperandNo, NumOps,
119 MIOperandNo += NumOps;
|
| DAGISelMatcherEmitter.cpp | 646 unsigned NumOps = P.getNumOperands();
649 ++NumOps; // Get the chained node too.
652 OS << " Result.resize(NextRes+" << NumOps << ");\n";
667 for (unsigned i = 0; i != NumOps; ++i)
|
