| /frameworks/opt/vcard/tests/src/com/android/vcard/tests/ |
| VCardParserTests.java | 37 private enum Order {
46 private final List<Order> mHistory = new ArrayList<Order>();
47 private final List<Order> mExpectedOrder = new ArrayList<Order>();
49 public MockVCardInterpreter addExpectedOrder(Order order) {
50 mExpectedOrder.add(order);
54 private void inspectOrder(Order order) {
[all...] |
| /external/llvm/lib/CodeGen/ |
| AllocationOrder.cpp | 1 //===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
10 // This file implements an allocation order for virtual registers.
12 // The preferred allocation order for a virtual register depends on allocation
43 // The remaining allocation order may depend on the hint.
44 ArrayRef<uint16_t> Order =
47 if (Order.empty())
50 // Copy the allocation order with reserved registers removed.
52 unsigned *P = new unsigned[Order.size()];
54 for (unsigned i = 0; i != Order.size(); ++i)
55 if (!RCI.isReserved(Order[i])
[all...] |
| RegisterClassInfo.cpp | 70 /// compute - Compute the preferred allocation order for RC with reserved
72 /// aliases ordered according to the CSR order specified by the target.
79 if (!RCI.Order)
80 RCI.Order.reset(new unsigned[NumRegs]);
86 // allocation order, we can simply use begin/end here.
90 // Remove reserved registers from the allocation order.
97 RCI.Order[N++] = PhysReg;
100 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
102 // CSR aliases go after the volatile registers, preserve the target's order.
103 std::copy(CSRAlias.begin(), CSRAlias.end(), &RCI.Order[N])
[all...] |
| RegAllocGreedy.cpp | 412 // Everything is allocated in long->short order. Long ranges that don't fit
439 AllocationOrder &Order,
441 Order.rewind();
443 while ((PhysReg = Order.next()))
446 if (!PhysReg || Order.isHint(PhysReg))
454 if (Order.isHint(Hint)) {
472 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost);
482 /// eviction policy defined by this function together with the allocation order
552 // larger allocation order.
625 /// @param Order Physregs to try
[all...] |
| ScheduleDAGInstrs.cpp | 373 ExitSU.addPred(SDep(SU, SDep::Order, Latency,
407 // Defs are pushed in the order they are visited and never reordered.
518 // in hope to trigger an assert downstream in order to
638 SUb->addPred(SDep(SUa, SDep::Order, /*Latency=*/0, /*Reg=*/0,
671 (*I)->addPred(SDep(SU, SDep::Order, Latency, /*Reg=*/0,
696 SUb->addPred(SDep(SUa, SDep::Order, TrueMemOrderLatency, /*Reg=*/0,
708 /// order. The instruction order A < B, implies that no edge exists from B to A.
716 /// MachineScheduler relies on initSUnits numbering the nodes by their order in
[all...] |
| RegAllocBasic.cpp | 229 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
230 while (unsigned PhysReg = Order.next()) {
|
| AggressiveAntiDepBreaker.cpp | 609 // order. If that register is available, and the corresponding
619 ArrayRef<unsigned> Order = RegClassInfo.getOrder(SuperRC);
620 if (Order.empty()) {
628 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size()));
631 unsigned EndR = ((OrigR == Order.size()) ? 0 : OrigR);
634 if (R == 0) R = Order.size();
636 const unsigned NewSuperReg = Order[R];
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SDNodeDbgValue.h | 50 unsigned Order;
55 unsigned O) : mdPtr(mdP), Offset(off), DL(dl), Order(O),
65 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) {
72 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) {
101 // Returns the SDNodeOrder. This is the order of the preceding node in the
103 unsigned getOrder() { return Order; }
|
| ScheduleDAGSDNodes.cpp | 205 /// outputs to ensure they are scheduled together and in order. This
245 // Sort them in increasing order.
267 // ensure they are scheduled in order of increasing addresses.
324 // Add all nodes in depth first order.
488 const SDep &dep = SDep(OpSU, isChain ? SDep::Order : SDep::Data,
706 unsigned Order) {
711 // order number right after the N.
719 if (!Order || DVOrder == ++Order) {
730 // ProcessSourceNode - Process nodes with source order numbers. These are adde
[all...] |
| /external/aac/libAACdec/src/ |
| aacdec_tns.h | 99 TNS_MAXIMUM_ORDER = 20, /* 12 for AAC-LC and AAC-SSR. Set to 20 for AAC-Main (AOT 1). Some broken encoders also do order 20 for AAC-LC :( */
113 UCHAR Order;
|
| aacdec_tns.cpp | 133 UCHAR n_filt,order; local
176 filter->Order = order = (UCHAR) FDKreadBits(bs, isLongFlag ? 5 : 3);
179 if (filter->Order > TNS_MAXIMUM_ORDER){
180 filter->Order = order = TNS_MAXIMUM_ORDER;
183 if (order)
200 for (i=0; i < order; i++)
216 static void CTns_Filter (FIXP_DBL *spec, int size, int inc, FIXP_TCC coeff [], int order)
218 // - Simple all-pole filter of order "order" defined b
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ScheduleDAG.h | 52 Order ///< Any other ordering dependency.
67 /// Order - Additional information about Order dependencies.
81 } Order;
109 assert(!isMustAlias && "isMustAlias only applies with SDep::Order!");
110 assert(!isArtificial && "isArtificial only applies with SDep::Order!");
113 case Order:
115 Contents.Order.isNormalMemory = isNormalMemory;
116 Contents.Order.isMustAlias = isMustAlias;
117 Contents.Order.isArtificial = isArtificial
[all...] |
| RegisterClassInfo.h | 32 OwningArrayPtr<unsigned> Order;
36 return makeArrayRef(Order.get(), NumRegs);
84 /// getOrder - Returns the preferred allocation order for RC. The order
122 /// Allocatable registers may show up in the allocation order of some virtual
|
| /external/icu4c/test/intltest/ |
| tscoll.h | 26 struct Order
28 int32_t order; member in struct:IntlTestCollator::Order
51 Order *getOrders(CollationElementIterator &iter, int32_t &orderLength);
|
| tscoll.cpp | 406 LocalArray<Order> orders(getOrders(iter, orderLength));
431 if (o != orders[index].order) {
435 while (index > 0 && orders[--index].order == 0) {
439 if (o != orders[index].order) {
440 errln("Mismatched order at index %d: 0x%0:8X vs. 0x%0:8X", index,
441 orders[index].order, o);
459 while (index != 0 && orders[index - 1].order == 0)
499 IntlTestCollator::Order *IntlTestCollator::getOrders(CollationElementIterator &iter, int32_t &orderLength)
503 LocalArray<Order> orders(new Order[maxSize])
507 int32_t order; local
[all...] |
| ssearch.cpp | 674 struct Order
676 int32_t order; member in struct:Order
689 void add(int32_t order, int32_t low, int32_t high);
690 const Order *get(int32_t index) const;
699 Order *list;
707 list = new Order[listMax];
716 int32_t order, low, high; local
732 list = new Order[listMax];
738 order = ucol_next(elems, &status);
741 if (order != UCOL_NULLORDER)
788 const Order *order = get(index); local
799 const Order *order = get(index); local
810 const Order *order = get(index); local
875 const Order *order = list.get(i); local
893 const Order *order = list.get(i); local
991 int32_t order, low, high; local
1116 uint64_t order; local
[all...] |
| /external/webkit/LayoutTests/http/conf/ |
| apache2-debian-httpd.conf | 188 # Note: The order in which modules are loaded is important. Don't change
189 # the order below without expert advice.
295 Order allow,deny
317 Order allow,deny
327 Order allow,deny
333 Order allow,deny
524 # Just list the languages in decreasing order of preference. We have
637 # Order deny,allow
|
| apache2-httpd.conf | 184 # Note: The order in which modules are loaded is important. Don't change
185 # the order below without expert advice.
316 Order allow,deny
338 Order allow,deny
348 Order allow,deny
354 Order allow,deny
545 # Just list the languages in decreasing order of preference. We have
658 # Order deny,allow
|
| apache2-msys-httpd.conf | 184 # Note: The order in which modules are loaded is important. Don't change
185 # the order below without expert advice.
317 Order allow,deny
339 Order allow,deny
349 Order allow,deny
355 Order allow,deny
546 # Just list the languages in decreasing order of preference. We have
659 # Order deny,allow
|
| cygwin-httpd.conf | 93 # in that order. The latter two files are now distributed empty, as it is
198 # Note: The order in which modules are loaded is important. Don't change
199 # the order below without expert advice.
242 # (static and shared ones) to achieve correct module execution order.
348 Order allow,deny
370 Order allow,deny
380 Order allow,deny
386 Order allow,deny
577 # Just list the languages in decreasing order of preference. We have
690 # Order deny,allo
[all...] |
| fedora-httpd.conf | 336 Order allow,deny
350 # Order allow,deny
354 # Order deny,allow
381 Order allow,deny
391 Order allow,deny
397 Order allow,deny
629 # Just list the languages in decreasing order of preference. We have
778 # Order deny,allow
790 # Order deny,allow
803 # Order deny,allo
[all...] |
| httpd.conf | 93 # in that order. The latter two files are now distributed empty, as it is
200 # Note: The order in which modules are loaded is important. Don't change
201 # the order below without expert advice.
245 # (static and shared ones) to achieve correct module execution order.
351 Order allow,deny
373 Order allow,deny
383 Order allow,deny
389 Order allow,deny
580 # Just list the languages in decreasing order of preference. We have
693 # Order deny,allo
[all...] |
| /external/llvm/lib/Target/ |
| TargetRegisterInfo.cpp | 119 ArrayRef<uint16_t> Order = RC->getRawAllocationOrder(MF);
120 for (unsigned i = 0; i != Order.size(); ++i)
121 R.set(Order[i]);
|
| /external/llvm/lib/Support/ |
| Dwarf.cpp | [all...] |
| /external/llvm/utils/TableGen/ |
| RegisterInfoEmitter.cpp | 590 // The list of overlaps doesn't need to have any particular order, and Reg
687 ArrayRef<Record*> Order = RC.getOrder();
696 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
697 Record *Reg = Order[i];
706 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
707 Record *Reg = Order[i];
864 ArrayRef<Record*> Order = RC.getOrder();
867 AllocatableRegs.insert(Order.begin(), Order.end());
[all...] |
