| /external/llvm/lib/CodeGen/ |
| LiveRegMatrix.cpp | 73 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI)
74 << " to " << PrintReg(PhysReg, TRI) << ':');
88 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI)
89 << " from " << PrintReg(PhysReg, TRI) << ':');
|
| RegAllocFast.cpp | 269 DEBUG(dbgs() << "Spilling " << PrintReg(LRI->VirtReg, TRI)
270 << " in " << PrintReg(LR.PhysReg, TRI));
433 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is already used in instr.\n");
442 DEBUG(dbgs() << PrintReg(VirtReg, TRI) << " corresponding "
443 << PrintReg(PhysReg, TRI) << " is reserved already.\n");
453 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is disabled.\n");
484 DEBUG(dbgs() << "Assigning " << PrintReg(LR.VirtReg, TRI) << " to "
485 << PrintReg(PhysReg, TRI) << "\n");
539 DEBUG(dbgs() << "Allocating " << PrintReg(VirtReg) << " from "
545 DEBUG(dbgs() << "\tRegister: " << PrintReg(*I, TRI) << "\n")
[all...] |
| VirtRegMap.cpp | 113 OS << '[' << PrintReg(Reg, TRI) << " -> "
114 << PrintReg(Virt2PhysMap[Reg], TRI) << "] "
122 OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
|
| RegAllocBase.cpp | 102 << ':' << PrintReg(VirtReg->reg) << ' ' << *VirtReg << '\n');
|
| RegisterClassInfo.cpp | 117 dbgs() << ' ' << PrintReg(RCI.Order[I], TRI);
|
| InlineSpiller.cpp | 315 OS << "spill " << PrintReg(SVI.SpillReg) << ':'
480 DEBUG(dbgs() << "Cached value " << PrintReg(UseReg) << ':'
485 DEBUG(dbgs() << "Tracing value " << PrintReg(UseReg) << ':'
497 DEBUG(dbgs() << " " << PrintReg(Reg) << ':' << VNI->id << '@' << VNI->def
584 DEBUG(dbgs() << "copy of " << PrintReg(SrcReg) << ':'
657 DEBUG(dbgs() << "Value " << PrintReg(Reg) << ':' << VNI->id << '@'
682 DEBUG(dbgs() << "Stale interval: " << PrintReg(SVI.SpillReg) << '\n');
689 DEBUG(dbgs() << "Stale value: " << PrintReg(SVI.SpillReg) << '\n');
[all...] |
| RegisterCoalescer.cpp | 449 DEBUG(dbgs() << "Extending: " << PrintReg(IntB.reg, TRI));
[all...] |
| RegAllocGreedy.cpp | 455 DEBUG(dbgs() << "missed hint " << PrintReg(Hint, TRI) << '\n');
470 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is available at cost " << Cost
595 DEBUG(dbgs() << "evicting " << PrintReg(PhysReg, TRI)
653 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " would clobber CSR "
654 << PrintReg(CSR, TRI) << '\n');
[all...] |
| MachineFunction.cpp | 323 OS << PrintReg(I->first, TRI);
325 OS << " in " << PrintReg(I->second, TRI);
335 OS << ' ' << PrintReg(*I, TRI);
|
| RegAllocPBQP.cpp | 488 DEBUG(dbgs() << "VREG " << PrintReg(vreg, tri) << " -> "
498 DEBUG(dbgs() << "VREG " << PrintReg(vreg, tri) << " -> SPILLED (Cost: "
506 DEBUG(dbgs() << PrintReg((*itr)->reg, tri) << " ");
|
| PHIElimination.cpp | 236 DEBUG(dbgs() << "Reusing " << PrintReg(IncomingReg) << " for " << *MPhi);
456 DEBUG(dbgs() << PrintReg(Reg) << " live-out before critical edge BB#"
|
| LiveIntervalUnion.cpp | 90 << PrintReg(SI.value()->reg, TRI);
|
| MachineVerifier.cpp | 401 *OS << PrintReg(LI.reg, TRI);
412 *OS << PrintReg(LI.reg, TRI);
[all...] |
| LiveRangeEdit.cpp | 376 DEBUG(dbgs() << "Inflated " << PrintReg(LI.reg) << " to "
|
| RegisterPressure.cpp | 70 dbgs() << PrintReg(LiveInRegs[i], TRI) << " ";
74 dbgs() << PrintReg(LiveOutRegs[i], TRI) << " ";
|
| MachineInstr.cpp | 267 OS << PrintReg(getReg(), TRI, getSubReg());
[all...] |
| ScheduleDAG.cpp | 316 dbgs() << " Reg=" << PrintReg(I->getReg(), G->TRI);
|
| LiveIntervalAnalysis.cpp | 148 OS << PrintReg(Reg) << " = " << getInterval(Reg) << '\n';
206 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, TRI));
[all...] |
| MachineBasicBlock.cpp | 288 OS << ' ' << PrintReg(*I, TRI);
[all...] |
| MachineTraceMetrics.cpp | [all...] |
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | [all...] |
| /external/llvm/lib/Target/ |
| TargetRegisterInfo.cpp | 30 void PrintReg::print(raw_ostream &OS) const {
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 426 OS << ' ' << PrintReg(R->getReg(), G ? G->getTarget().getRegisterInfo() :0);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonHardwareLoops.cpp | 158 if (isReg()) { OS << PrintReg(getReg()); }
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCCTRLoops.cpp | 171 if (isReg()) { OS << PrintReg(getReg()); }
|
