| /external/llvm/lib/Target/Hexagon/ |
| HexagonVarargsCallingConvention.h | 54 Hexagon::R5
110 Hexagon::R5
|
| HexagonISelLowering.cpp | 165 Hexagon::R5
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.cpp | 319 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
323 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
331 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
335 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
343 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
347 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
355 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
359 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
367 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
371 ARM::R1, ARM::R3, ARM::R5, ARM::R11
[all...] |
| ARMBaseRegisterInfo.h | 42 case R4: case R5: case R6: case R7:
|
| Thumb1FrameLowering.cpp | 88 case ARM::R5:
|
| ARMFrameLowering.cpp | 177 case ARM::R5:
[all...] |
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCBaseInfo.h | 36 case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5;
|
| /external/llvm/lib/Target/MBlaze/MCTargetDesc/ |
| MBlazeBaseInfo.h | 110 case MBlaze::R5 : return 5;
174 case 5 : return MBlaze::R5;
|
| /external/oprofile/module/ia64/ |
| IA64entry.h | 51 .spillsp r4, SW(R4)+16+(off); .spillsp r5, SW(R5)+16+(off); \
|
| /external/valgrind/main/coregrind/m_sigframe/ |
| sigframe-arm-linux.c | 143 SC2(r5,R5);
317 REST(r5,R5);
|
| /system/core/libpixelflinger/codeflinger/ |
| ARMAssemblerInterface.h | 50 R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15,
57 LIST(R0), LIST(R1), LIST(R2), LIST(R3), LIST(R4), LIST(R5), LIST(R6),
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMBaseInfo.h | 170 case R4: case R5: case R6: case R7:
|
| /external/valgrind/main/VEX/auxprogs/ |
| genoffsets.c | 154 GENOFFSET(ARM,arm,R5);
164 GENOFFSET(S390X,s390x,r5);
|
| /external/llvm/lib/Target/CellSPU/ |
| SPURegisterInfo.cpp | 59 case SPU::R5: return 5;
|
| SPUISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 65 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeFrameLowering.cpp | 186 case MBlaze::R5: FILoc = -4; break;
|
| MBlazeISelLowering.cpp | 661 MBlaze::R5, MBlaze::R6, MBlaze::R7,
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| /external/valgrind/main/memcheck/ |
| mc_machine.c | [all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /external/llvm/test/MC/ARM/ |
| basic-thumb2-instructions.s | 26 adc r5, r3, #0x87000000
36 @ CHECK: adc r5, r3, #2264924160 @ encoding: [0x43,0xf1,0x07,0x45]
43 adc r4, r5, r6
44 adcs r4, r5, r6
53 @ CHECK: adc.w r4, r5, r6 @ encoding: [0x45,0xeb,0x06,0x04]
54 @ CHECK: adcs.w r4, r5, r6 @ encoding: [0x55,0xeb,0x06,0x04]
69 addwne r5, r3, #1023
70 addeq r4, r5, #293
91 @ CHECK: addwne r5, r3, #1023 @ encoding: [0x03,0xf2,0xff,0x35]
92 @ CHECK: addweq r4, r5, #293 @ encoding: [0x05,0xf2,0x25,0x14
[all...] |
