| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.cpp | 59 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
125 case ARM::R7:
319 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
323 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
328 // FP is R7, R9 is available.
343 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
348 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
355 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
359 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
364 // FP is R7, R9 is not available
[all...] |
| ARMBaseRegisterInfo.h | 36 /// isARMArea1Register - Returns true if the register is a low register (r0-r7)
42 case R4: case R5: case R6: case R7:
46 // For iOS we want r7 and lr to be next to each other.
|
| Thumb1FrameLowering.cpp | 90 case ARM::R7:
|
| ARMFrameLowering.cpp | 179 case ARM::R7:
215 // For iOS, FP is R7, which has now been stored in spill area 1.
268 // Restore from fp only in ARM mode: e.g. sub sp, r7, #24
271 // mov sp, r7
397 // mov sp, r7
[all...] |
| ARMAsmPrinter.cpp | [all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCBaseInfo.h | 38 case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7;
|
| /external/llvm/lib/Target/MBlaze/MCTargetDesc/ |
| MBlazeBaseInfo.h | 112 case MBlaze::R7 : return 7;
176 case 7 : return MBlaze::R7;
|
| /external/oprofile/module/ia64/ |
| IA64entry.h | 52 .spillsp r6, SW(R6)+16+(off); .spillsp r7, SW(R7)+16+(off); \
|
| /external/valgrind/main/coregrind/m_sigframe/ |
| sigframe-arm-linux.c | 145 SC2(r7,R7);
319 REST(r7,R7);
|
| /system/core/libpixelflinger/codeflinger/ |
| ARMAssemblerInterface.h | 50 R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15,
58 LIST(R7), LIST(R8), LIST(R9), LIST(R10), LIST(R11), LIST(R12),
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMBaseInfo.h | 164 /// isARMLowRegister - Returns true if the register is a low register (r0-r7).
170 case R4: case R5: case R6: case R7:
|
| /external/valgrind/main/VEX/auxprogs/ |
| genoffsets.c | 155 GENOFFSET(ARM,arm,R7);
166 GENOFFSET(S390X,s390x,r7);
|
| /external/llvm/lib/Target/CellSPU/ |
| SPURegisterInfo.cpp | 61 case SPU::R7: return 7;
|
| SPUISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 65 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeFrameLowering.cpp | 188 case MBlaze::R7: FILoc = -12; break;
|
| MBlazeISelLowering.cpp | 661 MBlaze::R5, MBlaze::R6, MBlaze::R7,
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| /external/valgrind/main/memcheck/ |
| mc_machine.c | [all...] |
| /external/chromium/third_party/libjingle/source/talk/session/phone/testdata/ |
| video.rtpdump | [all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /external/llvm/test/MC/ARM/ |
| basic-thumb2-instructions.s | 23 adc r3, r7, #0x00550055
25 adc r9, r7, #0xa5a5a5a5
33 @ CHECK: adc r3, r7, #5570645 @ encoding: [0x47,0xf1,0x55,0x13]
35 @ CHECK: adc r9, r7, #2779096485 @ encoding: [0x47,0xf1,0xa5,0x39]
117 adds r7, r3, r1, lsl #31
125 @ CHECK: adds.w r7, r3, r1, lsl #31 @ encoding: [0x13,0xeb,0xc1,0x77]
163 ands r2, r1, r7, lsl #1
169 @ CHECK: ands.w r2, r1, r7, lsl #1 @ encoding: [0x11,0xea,0x47,0x02]
184 asrs.w r7, #5
195 @ CHECK: asrs.w r7, r7, #5 @ encoding: [0x5f,0xea,0x67,0x17
[all...] |
