| /external/llvm/lib/Target/CellSPU/ |
| SPUHazardRecognizers.h | 29 virtual HazardType getHazardType(SUnit *SU, int Stalls);
30 virtual void EmitInstruction(SUnit *SU);
|
| SPUHazardRecognizers.cpp | 38 SPUHazardRecognizer::getHazardType(SUnit *SU, int Stalls)
46 const SDNode *Node = SU->getNode()->getFlaggedMachineNode();
123 void SPUHazardRecognizer::EmitInstruction(SUnit *SU)
|
| /external/llvm/include/llvm/CodeGen/ |
| ResourcePriorityQueue.h | 88 void addNode(const SUnit *SU) {
92 void updateNode(const SUnit *SU) {}
108 /// Single cost function reflecting benefit of scheduling SU
110 signed SUSchedulingCost (SUnit *SU);
114 void initNumRegDefsLeft(SUnit *SU);
115 void updateNumRegDefsLeft(SUnit *SU);
116 signed regPressureDelta(SUnit *SU, bool RawPressure = false);
117 signed rawRegPressureDelta (SUnit *SU, unsigned RCId);
125 virtual void remove(SUnit *SU);
131 bool isResourceAvailable(SUnit *SU);
[all...] |
| LatencyPriorityQueue.h | 57 void addNode(const SUnit *SU) {
61 void updateNode(const SUnit *SU) {
84 virtual void remove(SUnit *SU);
95 void AdjustPriorityOfUnscheduledPreds(SUnit *SU);
96 SUnit *getSingleUnscheduledPred(SUnit *SU);
|
| ScheduleDAGInstrs.h | 102 SUnit *SU;
104 VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {}
114 SUnit *SU;
117 PhysRegSUOper(SUnit *su, int op): SU(su), OpIdx(op) {}
298 virtual void computeLatency(SUnit *SU);
311 virtual void dumpNode(const SUnit *SU) const
[all...] |
| ScheduleDAG.h | 179 void setSUnit(SUnit *SU) {
180 Dep.setPointer(SU);
472 virtual void addNode(const SUnit *SU) = 0;
473 virtual void updateNode(const SUnit *SU) = 0;
496 virtual void remove(SUnit *SU) = 0;
543 const MCInstrDesc *getInstrDesc(const SUnit *SU) const {
544 if (SU->isInstr()) return &SU->getInstr()->getDesc();
545 return getNodeDesc(SU->getNode());
554 virtual void dumpNode(const SUnit *SU) const = 0
[all...] |
| ScoreboardHazardRecognizer.h | 116 // Stalls provides an cycle offset at which SU will be scheduled. It will be
118 virtual HazardType getHazardType(SUnit *SU, int Stalls);
120 virtual void EmitInstruction(SUnit *SU);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ResourcePriorityQueue.cpp | 71 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) {
73 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
108 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU,
111 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
146 static unsigned numberCtrlDepsInSU(SUnit *SU) {
148 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
156 static unsigned numberCtrlPredInSU(SUnit *SU) {
652 SUnit *su = q.pop(); local
[all...] |
| ScheduleDAGRRList.cpp | 177 /// IsReachable - Checks if SU is reachable from TargetSU.
178 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) {
179 return Topo.IsReachable(SU, TargetSU);
182 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will
184 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) {
185 return Topo.WillCreateCycle(SU, TargetSU);
188 /// AddPred - adds a predecessor edge to SUnit SU.
191 void AddPred(SUnit *SU, const SDep &D) {
192 Topo.AddPred(SU, D.getSUnit());
193 SU->addPred(D)
[all...] |
| ScheduleDAGVLIW.cpp | 86 void releaseSucc(SUnit *SU, const SDep &D);
87 void releaseSuccessors(SUnit *SU);
88 void scheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
115 void ScheduleDAGVLIW::releaseSucc(SUnit *SU, const SDep &D) {
128 SuccSU->setDepthToAtLeast(SU->getDepth() + D.getLatency());
137 void ScheduleDAGVLIW::releaseSuccessors(SUnit *SU) {
139 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
144 releaseSucc(SU, *I);
151 void ScheduleDAGVLIW::scheduleNodeTopDown(SUnit *SU, unsigned CurCycle)
[all...] |
| ScheduleDAGFast.cpp | 80 /// AddPred - adds a predecessor edge to SUnit SU.
82 void AddPred(SUnit *SU, const SDep &D) {
83 SU->addPred(D);
86 /// RemovePred - removes a predecessor edge from SUnit SU.
88 void RemovePred(SUnit *SU, const SDep &D) {
89 SU->removePred(D);
93 void ReleasePred(SUnit *SU, SDep *PredEdge);
94 void ReleasePredecessors(SUnit *SU, unsigned CurCycle);
121 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su
[all...] |
| ScheduleDAGSDNodes.h | 92 void InitVRegCycleFlag(SUnit *SU);
96 void InitNumRegDefsLeft(SUnit *SU);
100 virtual void computeLatency(SUnit *SU);
119 virtual void dumpNode(const SUnit *SU) const;
123 virtual std::string getGraphNodeLabel(const SUnit *SU) const;
139 RegDefIter(const SUnit *SU, const ScheduleDAGSDNodes *SD);
173 void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap,
|
| ScheduleDAGSDNodes.cpp | 78 SUnit *SU = &SUnits.back();
83 SU->SchedulingPref = Sched::None;
85 SU->SchedulingPref = TLI.getSchedulingPreference(N);
86 return SU;
90 SUnit *SU = newSUnit(Old->getNode());
91 SU->OrigNode = Old->OrigNode;
92 SU->Latency = Old->Latency;
93 SU->isVRegCycle = Old->isVRegCycle;
94 SU->isCall = Old->isCall;
95 SU->isCallOp = Old->isCallOp
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonMachineScheduler.cpp | 64 void VLIWMachineScheduler::releaseSucc(SUnit *SU, SDep *SuccEdge) {
80 /// releaseSuccessors - Call releaseSucc on each of SU's successors.
81 void VLIWMachineScheduler::releaseSuccessors(SUnit *SU) {
82 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
84 releaseSucc(SU, &*I);
92 void VLIWMachineScheduler::releasePred(SUnit *SU, SDep *PredEdge) {
108 /// releasePredecessors - Call releasePred on each of SU's predecessors.
109 void VLIWMachineScheduler::releasePredecessors(SUnit *SU) {
110 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end()
[all...] |
| HexagonMachineScheduler.h | 61 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
65 virtual void releaseTopNode(SUnit *SU) = 0;
68 virtual void releaseBottomNode(SUnit *SU) = 0;
91 // SU is in this queue if it's NodeQueueID is a superset of this ID.
92 bool isInQueue(SUnit *SU) const { return (SU->NodeQueueId & ID); }
104 iterator find(SUnit *SU) {
105 return std::find(Queue.begin(), Queue.end(), SU);
108 void push(SUnit *SU) {
109 Queue.push_back(SU);
[all...] |
| /external/llvm/lib/CodeGen/ |
| LatencyPriorityQueue.cpp | 54 /// of SU, return it, otherwise return null.
55 SUnit *LatencyPriorityQueue::getSingleUnscheduledPred(SUnit *SU) {
57 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
72 void LatencyPriorityQueue::push(SUnit *SU) {
76 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
78 if (getSingleUnscheduledPred(I->getSUnit()) == SU)
81 NumNodesSolelyBlocking[SU->NodeNum] = NumNodesBlocking;
83 Queue.push_back(SU);
147 SUnit *su = q.pop(); local
[all...] |
| MachineScheduler.cpp | 309 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
313 virtual void releaseTopNode(SUnit *SU) = 0;
316 virtual void releaseBottomNode(SUnit *SU) = 0;
426 void releaseSucc(SUnit *SU, SDep *SuccEdge);
427 void releaseSuccessors(SUnit *SU);
428 void releasePred(SUnit *SU, SDep *PredEdge);
429 void releasePredecessors(SUnit *SU);
439 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) {
455 /// releaseSuccessors - Call releaseSucc on each of SU's successors.
456 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) {
[all...] |
| ScheduleDAGInstrs.cpp | 191 /// the exit SU to the register defs and use list. This is because we want to
233 /// MO is an operand of SU's instruction that defines a physical register. Add
234 /// data dependencies from SU to any uses of the physical register.
235 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
236 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
242 unsigned DataLatency = SU->Latency;
250 SUnit *UseSU = UseList[i].SU;
251 if (UseSU == SU)
275 SDep dep(SU, SDep::Data, LDataLatency, *Alias);
278 TII->computeOperandLatency(InstrItins, SU->getInstr(), OperIdx
[all...] |
| ScheduleDAG.cpp | 167 SUnit *SU = WorkList.pop_back_val();
168 SU->isDepthCurrent = false;
169 for (SUnit::const_succ_iterator I = SU->Succs.begin(),
170 E = SU->Succs.end(); I != E; ++I) {
183 SUnit *SU = WorkList.pop_back_val();
184 SU->isHeightCurrent = false;
185 for (SUnit::const_pred_iterator I = SU->Preds.begin(),
186 E = SU->Preds.end(); I != E; ++I) {
286 dbgs() << "SU(" << NodeNum << "): ";
311 dbgs() << "SU(" << I->getSUnit()->NodeNum << ")"
[all...] |
| ScoreboardHazardRecognizer.cpp | 118 ScoreboardHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
128 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
165 DEBUG(dbgs() << "SU(" << SU->NodeNum << "): ");
166 DEBUG(DAG->dumpNode(SU));
178 void ScoreboardHazardRecognizer::EmitInstruction(SUnit *SU) {
184 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
|
| ScheduleDAGPrinter.cpp | 75 std::string DOTGraphTraits<ScheduleDAG*>::getNodeLabel(const SUnit *SU,
77 return G->getGraphNodeLabel(SU);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.h | 33 virtual HazardType getHazardType(SUnit *SU, int Stalls);
34 virtual void EmitInstruction(SUnit *SU);
68 virtual HazardType getHazardType(SUnit *SU, int Stalls);
69 virtual void EmitInstruction(SUnit *SU);
|
| PPCHazardRecognizers.cpp | 26 void PPCScoreboardHazardRecognizer::EmitInstruction(SUnit *SU) {
27 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
32 ScoreboardHazardRecognizer::EmitInstruction(SU);
36 PPCScoreboardHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
37 return ScoreboardHazardRecognizer::getHazardType(SU, Stalls);
137 getHazardType(SUnit *SU, int Stalls) {
140 MachineInstr *MI = SU->getInstr();
197 void PPCHazardRecognizer970::EmitInstruction(SUnit *SU) {
198 MachineInstr *MI = SU->getInstr();
|
| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.cpp | 35 ARMHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
38 MachineInstr *MI = SU->getInstr();
70 return ScoreboardHazardRecognizer::getHazardType(SU, Stalls);
79 void ARMHazardRecognizer::EmitInstruction(SUnit *SU) {
80 MachineInstr *MI = SU->getInstr();
86 ScoreboardHazardRecognizer::EmitInstruction(SU);
|
| ARMHazardRecognizer.h | 47 virtual HazardType getHazardType(SUnit *SU, int Stalls);
49 virtual void EmitInstruction(SUnit *SU);
|
