| /external/llvm/lib/CodeGen/ |
| RegisterClassInfo.cpp | 31 RegisterClassInfo::RegisterClassInfo() : Tag(0), MF(0), TRI(0), CalleeSaved(0)
39 if (MF->getTarget().getRegisterInfo() != TRI) {
40 TRI = MF->getTarget().getRegisterInfo();
41 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
46 const uint16_t *CSR = TRI->getCalleeSavedRegs(MF);
51 CSRNum.resize(TRI->getNumRegs(), 0);
53 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
60 BitVector RR = TRI->getReservedRegs(*MF);
110 if (const TargetRegisterClass *Super = TRI->getLargestLegalSuperClass(RC))
117 dbgs() << ' ' << PrintReg(RCI.Order[I], TRI);
[all...] |
| LiveRegMatrix.cpp | 50 TRI = MF.getTarget().getRegisterInfo();
55 unsigned NumRegUnits = TRI->getNumRegUnits();
73 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI)
74 << " to " << PrintReg(PhysReg, TRI) << ':');
78 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
79 DEBUG(dbgs() << ' ' << PrintRegUnit(*Units, TRI));
88 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI)
89 << " from " << PrintReg(PhysReg, TRI) << ':');
91 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
92 DEBUG(dbgs() << ' ' << PrintRegUnit(*Units, TRI));
[all...] |
| RegisterCoalescer.h | 29 const TargetRegisterInfo &TRI;
62 CoalescerPair(const TargetRegisterInfo &tri)
63 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0),
69 const TargetRegisterInfo &tri)
70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
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| RegAllocBase.h | 61 const TargetRegisterInfo *TRI;
68 RegAllocBase(): TRI(0), MRI(0), VRM(0), LIS(0), Matrix(0) {}
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| RegisterScavenging.cpp | 40 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
45 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
77 TRI = TM.getRegisterInfo();
80 assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
90 NumPhysRegs = TRI->getNumRegs();
96 ReservedRegs = TRI->getReservedRegs(MF);
100 const uint16_t *CSRegs = TRI->getCalleeSavedRegs(&MF);
114 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
195 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
212 isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &
[all...] |
| MachineCopyPropagation.cpp | 34 const TargetRegisterInfo *TRI;
65 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
74 for (MCSubRegIterator SR(MappedDef, TRI); SR.isValid(); ++SR)
111 const TargetRegisterInfo *TRI) {
115 if (TRI->isSubRegister(SrcSrc, Def)) {
117 unsigned SubIdx = TRI->getSubRegIndex(SrcSrc, Def);
120 return SubIdx == TRI->getSubRegIndex(SrcDef, Src);
151 isNopCopy(CopyMI, Def, Src, TRI)) {
169 I->clearRegisterKills(Def, TRI);
179 for (MCRegAliasIterator AI(Src, TRI, true); AI.isValid(); ++AI)
[all...] |
| RegisterPressure.cpp | 30 const TargetRegisterInfo *TRI) {
31 unsigned Weight = TRI->getRegClassWeight(RC).RegWeight;
32 for (const int *PSet = TRI->getRegClassPressureSets(RC);
45 const TargetRegisterInfo *TRI) {
46 unsigned Weight = TRI->getRegClassWeight(RC).RegWeight;
47 for (const int *PSet = TRI->getRegClassPressureSets(RC);
56 const TargetRegisterInfo *TRI) {
57 increaseSetPressure(MaxSetPressure, MaxSetPressure, RC, TRI);
62 const TargetRegisterInfo *TRI) {
63 decreaseSetPressure(MaxSetPressure, RC, TRI);
[all...] |
| MachineRegisterInfo.cpp | 20 MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI)
21 : TRI(&TRI), IsSSA(true), TracksLiveness(true) {
24 UsedPhysRegs.resize(TRI.getNumRegs());
25 UsedPhysRegMask.resize(TRI.getNumRegs());
28 PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
29 memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
56 const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC);
69 const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC);
79 I->getRegClassConstraint(I.getOperandNo(), TII, TRI);
[all...] |
| AllocationOrder.cpp | 42 const TargetRegisterInfo &TRI = VRM.getTargetRegInfo();
45 TRI.getRawAllocationOrder(RC, HintPair.first, Hint,
60 Hint = TRI.ResolveRegAllocHint(HintPair.first, Hint,
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| InterferenceCache.h | 25 const TargetRegisterInfo *TRI;
112 void revalidate(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI);
115 bool valid(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI);
120 const TargetRegisterInfo *TRI,
150 InterferenceCache() : TRI(0), LIUArray(0), MF(0), RoundRobin(0) {}
|
| AggressiveAntiDepBreaker.cpp | 123 TRI(MF.getTarget().getRegisterInfo()),
129 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]);
139 dbgs() << " " << TRI->getName(r));
149 State = new AggressiveAntiDepState(TRI->getNumRegs(), BB);
160 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) {
176 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) {
189 for (const uint16_t *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) {
192 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
220 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
229 dbgs() << " " << TRI->getName(Reg) << "=g" <
[all...] |
| /external/llvm/lib/Target/ |
| TargetInstrInfo.cpp | 35 const TargetRegisterInfo *TRI,
42 return TRI->getPointerRegClass(MF, RegClass);
49 return TRI->getRegClass(RegClass);
|
| TargetRegisterInfo.cpp | 37 else if (TRI && Reg < TRI->getNumRegs())
38 OS << '%' << TRI->getName(Reg);
42 if (TRI)
43 OS << ':' << TRI->getSubRegIndexName(SubIdx);
50 // Generic printout when TRI is missing.
51 if (!TRI) {
57 if (Unit >= TRI->getNumRegUnits()) {
63 MCRegUnitRootIterator Roots(Unit, TRI);
65 OS << TRI->getName(*Roots)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.h | 32 const ARMBaseRegisterInfo &TRI;
41 const ARMBaseRegisterInfo &tri,
45 TRI(tri), STI(sti), LastMI(0) {}
|
| Thumb1FrameLowering.h | 41 const TargetRegisterInfo *TRI) const;
45 const TargetRegisterInfo *TRI) const;
|
| Thumb1InstrInfo.h | 50 const TargetRegisterInfo *TRI) const;
56 const TargetRegisterInfo *TRI) const;
|
| Thumb2InstrInfo.h | 52 const TargetRegisterInfo *TRI) const;
58 const TargetRegisterInfo *TRI) const;
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.h | 41 const TargetRegisterInfo *TRI) const;
45 const TargetRegisterInfo *TRI) const;
|
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.h | 36 const TargetRegisterInfo *TRI) const;
40 const TargetRegisterInfo *TRI) const;
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.h | 37 const TargetRegisterInfo *TRI) const;
42 const TargetRegisterInfo *TRI) const;
|
| HexagonFrameLowering.cpp | 213 unsigned uniqueSuperReg(unsigned Reg, const TargetRegisterInfo *TRI) {
214 MCSuperRegIterator SRI(Reg, TRI);
227 const TargetRegisterInfo *TRI) const {
248 unsigned SuperReg = uniqueSuperReg(Reg, TRI);
253 unsigned SuperRegNext = uniqueSuperReg(CSI[i+1].getReg(), TRI);
254 SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg);
261 CSI[i+1].getFrameIdx(), SuperRegClass, TRI);
267 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
269 TRI);
281 const TargetRegisterInfo *TRI) const
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16InstrInfo.h | 55 const TargetRegisterInfo *TRI) const;
61 const TargetRegisterInfo *TRI) const;
|
| Mips16FrameLowering.h | 33 const TargetRegisterInfo *TRI) const;
|
| MipsSEFrameLowering.h | 34 const TargetRegisterInfo *TRI) const;
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 678 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
679 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
699 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
700 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
707 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
708 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
714 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
715 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
722 const TargetRegisterInfo *TRI = NULL) const {
723 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1
[all...] |
