Home | History | Annotate | Download | only in CodeGen
      1 //===-- RegAllocBase.h - basic regalloc interface and driver --*- C++ -*---===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file defines the RegAllocBase class, which is the skeleton of a basic
     11 // register allocation algorithm and interface for extending it. It provides the
     12 // building blocks on which to construct other experimental allocators and test
     13 // the validity of two principles:
     14 //
     15 // - If virtual and physical register liveness is modeled using intervals, then
     16 // on-the-fly interference checking is cheap. Furthermore, interferences can be
     17 // lazily cached and reused.
     18 //
     19 // - Register allocation complexity, and generated code performance is
     20 // determined by the effectiveness of live range splitting rather than optimal
     21 // coloring.
     22 //
     23 // Following the first principle, interfering checking revolves around the
     24 // LiveIntervalUnion data structure.
     25 //
     26 // To fulfill the second principle, the basic allocator provides a driver for
     27 // incremental splitting. It essentially punts on the problem of register
     28 // coloring, instead driving the assignment of virtual to physical registers by
     29 // the cost of splitting. The basic allocator allows for heuristic reassignment
     30 // of registers, if a more sophisticated allocator chooses to do that.
     31 //
     32 // This framework provides a way to engineer the compile time vs. code
     33 // quality trade-off without relying on a particular theoretical solver.
     34 //
     35 //===----------------------------------------------------------------------===//
     36 
     37 #ifndef LLVM_CODEGEN_REGALLOCBASE
     38 #define LLVM_CODEGEN_REGALLOCBASE
     39 
     40 #include "LiveIntervalUnion.h"
     41 #include "llvm/CodeGen/RegisterClassInfo.h"
     42 #include "llvm/ADT/OwningPtr.h"
     43 
     44 namespace llvm {
     45 
     46 template<typename T> class SmallVectorImpl;
     47 class TargetRegisterInfo;
     48 class VirtRegMap;
     49 class LiveIntervals;
     50 class LiveRegMatrix;
     51 class Spiller;
     52 
     53 /// RegAllocBase provides the register allocation driver and interface that can
     54 /// be extended to add interesting heuristics.
     55 ///
     56 /// Register allocators must override the selectOrSplit() method to implement
     57 /// live range splitting. They must also override enqueue/dequeue to provide an
     58 /// assignment order.
     59 class RegAllocBase {
     60 protected:
     61   const TargetRegisterInfo *TRI;
     62   MachineRegisterInfo *MRI;
     63   VirtRegMap *VRM;
     64   LiveIntervals *LIS;
     65   LiveRegMatrix *Matrix;
     66   RegisterClassInfo RegClassInfo;
     67 
     68   RegAllocBase(): TRI(0), MRI(0), VRM(0), LIS(0), Matrix(0) {}
     69 
     70   virtual ~RegAllocBase() {}
     71 
     72   // A RegAlloc pass should call this before allocatePhysRegs.
     73   void init(VirtRegMap &vrm, LiveIntervals &lis, LiveRegMatrix &mat);
     74 
     75   // The top-level driver. The output is a VirtRegMap that us updated with
     76   // physical register assignments.
     77   void allocatePhysRegs();
     78 
     79   // Get a temporary reference to a Spiller instance.
     80   virtual Spiller &spiller() = 0;
     81 
     82   /// enqueue - Add VirtReg to the priority queue of unassigned registers.
     83   virtual void enqueue(LiveInterval *LI) = 0;
     84 
     85   /// dequeue - Return the next unassigned register, or NULL.
     86   virtual LiveInterval *dequeue() = 0;
     87 
     88   // A RegAlloc pass should override this to provide the allocation heuristics.
     89   // Each call must guarantee forward progess by returning an available PhysReg
     90   // or new set of split live virtual registers. It is up to the splitter to
     91   // converge quickly toward fully spilled live ranges.
     92   virtual unsigned selectOrSplit(LiveInterval &VirtReg,
     93                                  SmallVectorImpl<LiveInterval*> &splitLVRs) = 0;
     94 
     95   // Use this group name for NamedRegionTimer.
     96   static const char *TimerGroupName;
     97 
     98 public:
     99   /// VerifyEnabled - True when -verify-regalloc is given.
    100   static bool VerifyEnabled;
    101 
    102 private:
    103   void seedLiveRegs();
    104 };
    105 
    106 } // end namespace llvm
    107 
    108 #endif // !defined(LLVM_CODEGEN_REGALLOCBASE)
    109