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      1 //===-- RegAllocBasic.cpp - Basic Register Allocator ----------------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file defines the RABasic function pass, which provides a minimal
     11 // implementation of the basic register allocator.
     12 //
     13 //===----------------------------------------------------------------------===//
     14 
     15 #define DEBUG_TYPE "regalloc"
     16 #include "AllocationOrder.h"
     17 #include "RegAllocBase.h"
     18 #include "LiveDebugVariables.h"
     19 #include "Spiller.h"
     20 #include "VirtRegMap.h"
     21 #include "LiveRegMatrix.h"
     22 #include "llvm/Analysis/AliasAnalysis.h"
     23 #include "llvm/PassAnalysisSupport.h"
     24 #include "llvm/CodeGen/CalcSpillWeights.h"
     25 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
     26 #include "llvm/CodeGen/LiveRangeEdit.h"
     27 #include "llvm/CodeGen/LiveStackAnalysis.h"
     28 #include "llvm/CodeGen/MachineFunctionPass.h"
     29 #include "llvm/CodeGen/MachineInstr.h"
     30 #include "llvm/CodeGen/MachineLoopInfo.h"
     31 #include "llvm/CodeGen/MachineRegisterInfo.h"
     32 #include "llvm/CodeGen/Passes.h"
     33 #include "llvm/CodeGen/RegAllocRegistry.h"
     34 #include "llvm/Target/TargetMachine.h"
     35 #include "llvm/Target/TargetOptions.h"
     36 #include "llvm/Target/TargetRegisterInfo.h"
     37 #include "llvm/Support/Debug.h"
     38 #include "llvm/Support/raw_ostream.h"
     39 
     40 #include <cstdlib>
     41 #include <queue>
     42 
     43 using namespace llvm;
     44 
     45 static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
     46                                       createBasicRegisterAllocator);
     47 
     48 namespace {
     49   struct CompSpillWeight {
     50     bool operator()(LiveInterval *A, LiveInterval *B) const {
     51       return A->weight < B->weight;
     52     }
     53   };
     54 }
     55 
     56 namespace {
     57 /// RABasic provides a minimal implementation of the basic register allocation
     58 /// algorithm. It prioritizes live virtual registers by spill weight and spills
     59 /// whenever a register is unavailable. This is not practical in production but
     60 /// provides a useful baseline both for measuring other allocators and comparing
     61 /// the speed of the basic algorithm against other styles of allocators.
     62 class RABasic : public MachineFunctionPass, public RegAllocBase
     63 {
     64   // context
     65   MachineFunction *MF;
     66 
     67   // state
     68   std::auto_ptr<Spiller> SpillerInstance;
     69   std::priority_queue<LiveInterval*, std::vector<LiveInterval*>,
     70                       CompSpillWeight> Queue;
     71 
     72   // Scratch space.  Allocated here to avoid repeated malloc calls in
     73   // selectOrSplit().
     74   BitVector UsableRegs;
     75 
     76 public:
     77   RABasic();
     78 
     79   /// Return the pass name.
     80   virtual const char* getPassName() const {
     81     return "Basic Register Allocator";
     82   }
     83 
     84   /// RABasic analysis usage.
     85   virtual void getAnalysisUsage(AnalysisUsage &AU) const;
     86 
     87   virtual void releaseMemory();
     88 
     89   virtual Spiller &spiller() { return *SpillerInstance; }
     90 
     91   virtual float getPriority(LiveInterval *LI) { return LI->weight; }
     92 
     93   virtual void enqueue(LiveInterval *LI) {
     94     Queue.push(LI);
     95   }
     96 
     97   virtual LiveInterval *dequeue() {
     98     if (Queue.empty())
     99       return 0;
    100     LiveInterval *LI = Queue.top();
    101     Queue.pop();
    102     return LI;
    103   }
    104 
    105   virtual unsigned selectOrSplit(LiveInterval &VirtReg,
    106                                  SmallVectorImpl<LiveInterval*> &SplitVRegs);
    107 
    108   /// Perform register allocation.
    109   virtual bool runOnMachineFunction(MachineFunction &mf);
    110 
    111   // Helper for spilling all live virtual registers currently unified under preg
    112   // that interfere with the most recently queried lvr.  Return true if spilling
    113   // was successful, and append any new spilled/split intervals to splitLVRs.
    114   bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
    115                           SmallVectorImpl<LiveInterval*> &SplitVRegs);
    116 
    117   static char ID;
    118 };
    119 
    120 char RABasic::ID = 0;
    121 
    122 } // end anonymous namespace
    123 
    124 RABasic::RABasic(): MachineFunctionPass(ID) {
    125   initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
    126   initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
    127   initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
    128   initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
    129   initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
    130   initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
    131   initializeLiveStacksPass(*PassRegistry::getPassRegistry());
    132   initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
    133   initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
    134   initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
    135   initializeLiveRegMatrixPass(*PassRegistry::getPassRegistry());
    136 }
    137 
    138 void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
    139   AU.setPreservesCFG();
    140   AU.addRequired<AliasAnalysis>();
    141   AU.addPreserved<AliasAnalysis>();
    142   AU.addRequired<LiveIntervals>();
    143   AU.addPreserved<LiveIntervals>();
    144   AU.addPreserved<SlotIndexes>();
    145   AU.addRequired<LiveDebugVariables>();
    146   AU.addPreserved<LiveDebugVariables>();
    147   AU.addRequired<CalculateSpillWeights>();
    148   AU.addRequired<LiveStacks>();
    149   AU.addPreserved<LiveStacks>();
    150   AU.addRequiredID(MachineDominatorsID);
    151   AU.addPreservedID(MachineDominatorsID);
    152   AU.addRequired<MachineLoopInfo>();
    153   AU.addPreserved<MachineLoopInfo>();
    154   AU.addRequired<VirtRegMap>();
    155   AU.addPreserved<VirtRegMap>();
    156   AU.addRequired<LiveRegMatrix>();
    157   AU.addPreserved<LiveRegMatrix>();
    158   MachineFunctionPass::getAnalysisUsage(AU);
    159 }
    160 
    161 void RABasic::releaseMemory() {
    162   SpillerInstance.reset(0);
    163 }
    164 
    165 
    166 // Spill or split all live virtual registers currently unified under PhysReg
    167 // that interfere with VirtReg. The newly spilled or split live intervals are
    168 // returned by appending them to SplitVRegs.
    169 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
    170                                  SmallVectorImpl<LiveInterval*> &SplitVRegs) {
    171   // Record each interference and determine if all are spillable before mutating
    172   // either the union or live intervals.
    173   SmallVector<LiveInterval*, 8> Intfs;
    174 
    175   // Collect interferences assigned to any alias of the physical register.
    176   for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
    177     LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
    178     Q.collectInterferingVRegs();
    179     if (Q.seenUnspillableVReg())
    180       return false;
    181     for (unsigned i = Q.interferingVRegs().size(); i; --i) {
    182       LiveInterval *Intf = Q.interferingVRegs()[i - 1];
    183       if (!Intf->isSpillable() || Intf->weight > VirtReg.weight)
    184         return false;
    185       Intfs.push_back(Intf);
    186     }
    187   }
    188   DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) <<
    189         " interferences with " << VirtReg << "\n");
    190   assert(!Intfs.empty() && "expected interference");
    191 
    192   // Spill each interfering vreg allocated to PhysReg or an alias.
    193   for (unsigned i = 0, e = Intfs.size(); i != e; ++i) {
    194     LiveInterval &Spill = *Intfs[i];
    195 
    196     // Skip duplicates.
    197     if (!VRM->hasPhys(Spill.reg))
    198       continue;
    199 
    200     // Deallocate the interfering vreg by removing it from the union.
    201     // A LiveInterval instance may not be in a union during modification!
    202     Matrix->unassign(Spill);
    203 
    204     // Spill the extracted interval.
    205     LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM);
    206     spiller().spill(LRE);
    207   }
    208   return true;
    209 }
    210 
    211 // Driver for the register assignment and splitting heuristics.
    212 // Manages iteration over the LiveIntervalUnions.
    213 //
    214 // This is a minimal implementation of register assignment and splitting that
    215 // spills whenever we run out of registers.
    216 //
    217 // selectOrSplit can only be called once per live virtual register. We then do a
    218 // single interference test for each register the correct class until we find an
    219 // available register. So, the number of interference tests in the worst case is
    220 // |vregs| * |machineregs|. And since the number of interference tests is
    221 // minimal, there is no value in caching them outside the scope of
    222 // selectOrSplit().
    223 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
    224                                 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
    225   // Populate a list of physical register spill candidates.
    226   SmallVector<unsigned, 8> PhysRegSpillCands;
    227 
    228   // Check for an available register in this class.
    229   AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
    230   while (unsigned PhysReg = Order.next()) {
    231     // Check for interference in PhysReg
    232     switch (Matrix->checkInterference(VirtReg, PhysReg)) {
    233     case LiveRegMatrix::IK_Free:
    234       // PhysReg is available, allocate it.
    235       return PhysReg;
    236 
    237     case LiveRegMatrix::IK_VirtReg:
    238       // Only virtual registers in the way, we may be able to spill them.
    239       PhysRegSpillCands.push_back(PhysReg);
    240       continue;
    241 
    242     default:
    243       // RegMask or RegUnit interference.
    244       continue;
    245     }
    246   }
    247 
    248   // Try to spill another interfering reg with less spill weight.
    249   for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(),
    250        PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
    251     if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs))
    252       continue;
    253 
    254     assert(!Matrix->checkInterference(VirtReg, *PhysRegI) &&
    255            "Interference after spill.");
    256     // Tell the caller to allocate to this newly freed physical register.
    257     return *PhysRegI;
    258   }
    259 
    260   // No other spill candidates were found, so spill the current VirtReg.
    261   DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
    262   if (!VirtReg.isSpillable())
    263     return ~0u;
    264   LiveRangeEdit LRE(&VirtReg, SplitVRegs, *MF, *LIS, VRM);
    265   spiller().spill(LRE);
    266 
    267   // The live virtual register requesting allocation was spilled, so tell
    268   // the caller not to allocate anything during this round.
    269   return 0;
    270 }
    271 
    272 bool RABasic::runOnMachineFunction(MachineFunction &mf) {
    273   DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n"
    274                << "********** Function: "
    275                << mf.getName() << '\n');
    276 
    277   MF = &mf;
    278   RegAllocBase::init(getAnalysis<VirtRegMap>(),
    279                      getAnalysis<LiveIntervals>(),
    280                      getAnalysis<LiveRegMatrix>());
    281   SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
    282 
    283   allocatePhysRegs();
    284 
    285   // Diagnostic output before rewriting
    286   DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n");
    287 
    288   releaseMemory();
    289   return true;
    290 }
    291 
    292 FunctionPass* llvm::createBasicRegisterAllocator()
    293 {
    294   return new RABasic();
    295 }
    296