| /external/llvm/include/llvm/CodeGen/ |
| CalcSpillWeights.h | 44 LiveIntervals &LIS;
48 VirtRegAuxInfo(MachineFunction &mf, LiveIntervals &lis,
50 MF(mf), LIS(lis), Loops(loops) {}
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| MachineScheduler.h | 49 LiveIntervals *LIS;
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| LiveRangeEdit.h | 61 LiveIntervals &LIS;
98 /// @param lis The collection of all live intervals in this function.
105 LiveIntervals &lis,
109 MRI(MF.getRegInfo()), LIS(lis), VRM(vrm),
189 /// to erase it from LIS.
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| RegisterPressure.h | 140 const LiveIntervals *LIS;
149 /// or RegisterPressure. If requireIntervals is false, LIS are ignored.
165 MF(0), TRI(0), RCI(0), LIS(0), MBB(0), P(rp), RequireIntervals(true) {}
168 MF(0), TRI(0), RCI(0), LIS(0), MBB(0), P(rp), RequireIntervals(false) {}
171 const LiveIntervals *lis, const MachineBasicBlock *mbb,
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| ScheduleDAGInstrs.h | 182 LiveIntervals *LIS;
252 LiveIntervals *LIS = 0);
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| /external/llvm/lib/CodeGen/ |
| RegAllocBase.h | 64 LiveIntervals *LIS;
68 RegAllocBase(): TRI(0), MRI(0), VRM(0), LIS(0), Matrix(0) {}
73 void init(VirtRegMap &vrm, LiveIntervals &lis, LiveRegMatrix &mat);
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| LiveRegMatrix.h | 43 LiveIntervals *LIS;
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| CalcSpillWeights.cpp | 46 LiveIntervals &LIS = getAnalysis<LiveIntervals>();
48 VirtRegAuxInfo VRAI(MF, LIS, getAnalysis<MachineLoopInfo>());
53 VRAI.CalculateWeightAndHint(LIS.getInterval(Reg));
91 const LiveIntervals &LIS,
101 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
104 if (!TII.isTriviallyReMaterializable(MI, LIS.getAliasAnalysis()))
153 if (writes && isExiting && LIS.isLiveOutOfMBB(li, mbb))
167 if (hweight > bestPhys && LIS.isAllocatable(hint))
189 if (li.isZeroLength(LIS.getSlotIndexes())) {
198 if (isRematerializable(li, LIS, *MF.getTarget().getInstrInfo())
[all...] |
| VirtRegMap.cpp | 152 LiveIntervals *LIS;
197 LIS = &getAnalysis<LiveIntervals>();
205 LIS->addKillFlags(VRM);
231 LiveInterval &LI = LIS->getInterval(VirtReg);
232 if (LI.empty() || LIS->intervalIsInOneMBB(LI))
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| InterferenceCache.h | 57 /// LIS - Used for accessing register mask interference maps.
58 LiveIntervals *LIS;
96 Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(0), LIS(0) {}
98 void clear(MachineFunction *mf, SlotIndexes *indexes, LiveIntervals *lis) {
103 LIS = lis;
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| SplitKit.h | 45 const LiveIntervals &LIS;
119 SplitAnalysis(const VirtRegMap &vrm, const LiveIntervals &lis,
212 LiveIntervals &LIS;
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| LiveDebugVariables.cpp | 129 LiveIntervals &LIS, const TargetInstrInfo &TII);
223 /// @param LIS Live intervals analysis.
228 LiveIntervals &LIS, MachineDominatorTree &MDT,
242 LiveIntervals &LIS);
247 LiveIntervals &LIS, MachineDominatorTree &MDT,
264 LiveIntervals &LIS, const TargetInstrInfo &TRI);
284 LiveIntervals *LIS;
470 LIS->getMBBStartIdx(MBB) :
471 LIS->getInstructionIndex(llvm::prior(MBBI)).getRegSlot();
488 LiveIntervals &LIS, MachineDominatorTree &MDT
[all...] |
| RegAllocPBQP.cpp | 137 LiveIntervals *lis; member in class:__anon10253::RegAllocPBQP
191 const LiveIntervals *lis,
195 LiveIntervals *LIS = const_cast<LiveIntervals*>(lis);
218 LiveInterval *vregLI = &LIS->getInterval(vreg);
222 LIS->checkRegMaskInterference(*vregLI, regMaskOverlaps);
240 if (vregLI->overlaps(LIS->getRegUnit(*Units))) {
268 const LiveInterval &l1 = lis->getInterval(vr1);
274 const LiveInterval &l2 = lis->getInterval(vr2);
319 const LiveIntervals *lis,
[all...] |
| InlineSpiller.cpp | 56 LiveIntervals &LIS;
140 LIS(pass.getAnalysis<LiveIntervals>()),
232 if (SnipLI.getNumValNums() > 2 || !LIS.intervalIsInOneMBB(SnipLI))
282 LiveInterval &SnipLI = LIS.getInterval(SnipReg);
368 SV.SpillMBB = LIS.getMBBFromIndex(SV.SpillVNI->def);
386 DepSV.SpillMBB = LIS.getMBBFromIndex(DepSV.SpillVNI->def);
526 LiveInterval &LI = LIS.getInterval(Reg);
527 LiveInterval &OrigLI = LIS.getInterval(Original);
572 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
578 LiveInterval &SrcLI = LIS.getInterval(SrcReg)
[all...] |
| LiveIntervalAnalysis.cpp | [all...] |
| RegisterCoalescer.cpp | 77 LiveIntervals *LIS;
372 LiveRangeEdit(0, NewRegs, *MF, *LIS, 0, this).eliminateDeadDefs(DeadDefs);
402 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
404 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
405 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
427 MachineInstr *ACopyMI = LIS->getInstructionFromIndex(AValNo->def);
440 LIS->getInstructionFromIndex(ValLR->end.getPrevSlot());
479 LIS->shrinkToUses(&IntA);
493 if (LIS->hasPHIKill(IntA, AValNo))
542 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot()
[all...] |
| TwoAddressInstructionPass.cpp | 71 LiveIntervals *LIS;
295 if (LIS)
296 LIS->handleMove(MI);
846 if (LIS)
847 LIS->handleMove(MI);
[all...] |
