| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 119 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
125 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
129 void EmitSegmentOverridePrefix(uint64_t TSFlags, unsigned &CurByte,
133 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
155 /// in an instruction with the specified TSFlags.
156 static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
157 unsigned Size = X86II::getSizeOfImm(TSFlags);
158 bool isPCRel = X86II::isImmPCRel(TSFlags);
299 uint64_t TSFlags, unsigned &CurByte,
327 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0
[all...] |
| X86BaseInfo.h | 484 inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) {
485 return TSFlags >> X86II::OpcodeShift;
488 inline bool hasImm(uint64_t TSFlags) {
489 return (TSFlags & X86II::ImmMask) != 0;
492 /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field
494 inline unsigned getSizeOfImm(uint64_t TSFlags) {
495 switch (TSFlags & X86II::ImmMask) {
508 /// TSFlags indicates that it is pc relative.
509 inline unsigned isImmPCRel(uint64_t TSFlags) {
510 switch (TSFlags & X86II::ImmMask)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.cpp | 99 uint64_t TSFlags = MCID.TSFlags;
101 isFirst = TSFlags & PPCII::PPC970_First;
102 isSingle = TSFlags & PPCII::PPC970_Single;
103 isCracked = TSFlags & PPCII::PPC970_Cracked;
104 return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask);
|
| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.cpp | 23 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
44 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
51 (LastMCID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) {
|
| MLxExpansionPass.cpp | 141 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
286 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
|
| ARMCodeEmitter.cpp | 483 unsigned Reloc = ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
563 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
[all...] |
| ARMBaseRegisterInfo.cpp | 805 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
[all...] |
| ARMBaseInstrInfo.cpp | 127 uint64_t TSFlags = MI->getDesc().TSFlags;
129 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
146 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
526 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
[all...] |
| Thumb2InstrInfo.cpp | 393 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
|
| Thumb1RegisterInfo.cpp | 395 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
|
| ARMFrameLowering.cpp | [all...] |
| ARMFastISel.cpp | 252 if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86CodeEmitter.cpp | 70 void emitOpcodePrefix(uint64_t TSFlags, int MemOperand,
74 void emitVEXOpcodePrefix(uint64_t TSFlags, int MemOperand,
78 void emitSegmentOverridePrefix(uint64_t TSFlags,
164 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
166 if (Desc.TSFlags & X86II::REX_W)
185 switch (Desc.TSFlags & X86II::FormMask) {
654 void Emitter<CodeEmitter>::emitOpcodePrefix(uint64_t TSFlags,
659 if (Desc->TSFlags & X86II::LOCK)
663 emitSegmentOverridePrefix(TSFlags, MemOperand, MI);
666 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP
[all...] |
| X86FloatingPoint.cpp | 416 uint64_t Flags = MI->getDesc().TSFlags;
[all...] |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.cpp | 116 // Look for the appropriate part of TSFlags
119 unsigned TSFlags = (MI.getDesc().TSFlags & NVPTX::SimpleMoveMask) >>
121 isMove = (TSFlags == 1);
162 unsigned TSFlags = (MI.getDesc().TSFlags & NVPTX::isLoadMask) >>
164 isLoad = (TSFlags == 1);
173 unsigned TSFlags = (MI.getDesc().TSFlags & NVPTX::isStoreMask) >>
175 isStore = (TSFlags == 1)
[all...] |
| VectorElementize.cpp | 133 #define VECINST(x) ((((x)->getDesc().TSFlags) & NVPTX::VecInstTypeMask) \
147 unsigned TSFlags = (mi->getDesc().TSFlags & NVPTX::SimpleMoveMask)
149 return (TSFlags == 1);
[all...] |
| /external/llvm/lib/Target/MBlaze/MCTargetDesc/ |
| MBlazeMCCodeEmitter.cpp | 182 uint64_t TSFlags = Desc.TSFlags;
189 switch ((TSFlags & MBlazeII::FormMask)) {
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCCodeEmitter.cpp | 125 uint64_t TSFlags = Desc.TSFlags;
129 if ((TSFlags & MipsII::FormMask) == MipsII::Pseudo)
|
| /external/llvm/lib/Target/Mips/ |
| MipsCodeEmitter.cpp | 159 uint64_t TSFlags = MI.getDesc().TSFlags;
160 uint64_t Form = TSFlags & MipsII::FormMask;
383 if ((MI.getDesc().TSFlags & MipsII::FormMask) == MipsII::Pseudo)
|
| /external/llvm/include/llvm/MC/ |
| MCInstrDesc.h | 142 uint64_t TSFlags; // Target Specific Flag values
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 295 switch (Desc.TSFlags & MSP430II::SizeMask) {
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | [all...] |
| /external/llvm/lib/Target/MBlaze/Disassembler/ |
| MBlazeDisassembler.cpp | 537 uint64_t tsFlags = MBlazeInsts[opcode].TSFlags;
538 switch ((tsFlags & MBlazeII::FormMask)) {
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | [all...] |
