| /external/llvm/lib/Target/X86/Utils/ |
| X86ShuffleDecode.h | 38 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
40 void DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
44 /// DecodeSHUFPMask - This decodes the shuffle masks for shufp*. VT indicates
47 void DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
50 /// and punpckh*. VT indicates the type of the vector allowing it to handle
52 void DecodeUNPCKHMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
55 /// and punpckl*. VT indicates the type of the vector allowing it to handle
57 void DecodeUNPCKLMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
60 void DecodeVPERM2X128Mask(MVT VT, unsigned Imm,
64 /// No VT provided since it only works on 256-bit, 4 element vectors
[all...] |
| X86ShuffleDecode.cpp | 65 /// VT indicates the type of the vector allowing it to handle different
67 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) {
68 unsigned NumElts = VT.getVectorNumElements();
70 unsigned NumLanes = VT.getSizeInBits() / 128;
83 void DecodePSHUFHWMask(MVT VT, unsigned Imm,
85 unsigned NumElts = VT.getVectorNumElements();
99 void DecodePSHUFLWMask(MVT VT, unsigned Imm,
101 unsigned NumElts = VT.getVectorNumElements();
115 /// DecodeSHUFPMask - This decodes the shuffle masks for shufp*. VT indicates
118 void DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask)
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 187 virtual EVT getSetCCResultType(EVT VT) const;
222 virtual const TargetRegisterClass *getRegClassFor(EVT VT) const {
223 assert(VT.isSimple() && "getRegClassFor called on illegal type!");
224 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
234 virtual const TargetRegisterClass *getRepRegClassFor(EVT VT) const {
235 assert(VT.isSimple() && "getRepRegClassFor called on illegal type!");
236 const TargetRegisterClass *RC = RepRegClassForVT[VT.getSimpleVT().SimpleTy];
242 virtual uint8_t getRepRegClassCostFor(EVT VT) const {
243 assert(VT.isSimple() && "getRepRegClassCostFor called on illegal type!");
244 return RepRegClassCostForVT[VT.getSimpleVT().SimpleTy]
[all...] |
| TargetCallingConv.h | 113 MVT VT;
116 InputArg() : VT(MVT::Other), Used(false) {}
117 InputArg(ArgFlagsTy flags, EVT vt, bool used)
119 VT = vt.getSimpleVT();
129 MVT VT;
135 OutputArg(ArgFlagsTy flags, EVT vt, bool isfixed)
137 VT = vt.getSimpleVT();
|
| /libcore/luni/src/main/java/java/util/ |
| EnumMap.java | 51 private static class Entry<KT extends Enum<KT>, VT> extends
52 MapEntry<KT, VT> {
53 private final EnumMap<KT, VT> enumMap;
57 Entry(KT theKey, VT theValue, EnumMap<KT, VT> em) {
71 Map.Entry<KT, VT> entry = (Map.Entry<KT, VT>) object;
102 public VT getValue() {
104 return (VT) enumMap.values[ordinal];
109 public VT setValue(VT value)
[all...] |
| MapEntry.java | 28 interface Type<RT, KT, VT> {
29 RT get(MapEntry<KT, VT> entry);
|
| IdentityHashMap.java | 129 static class IdentityHashMapIterator<E, KT, VT> implements Iterator<E> {
135 final IdentityHashMap<KT, VT> associatedMap;
139 final MapEntry.Type<E, KT, VT> type;
143 IdentityHashMapIterator(MapEntry.Type<E, KT, VT> value,
144 IdentityHashMap<KT, VT> hm) {
174 IdentityHashMapEntry<KT, VT> result = associatedMap
196 static class IdentityHashMapEntrySet<KT, VT> extends
197 AbstractSet<Map.Entry<KT, VT>> {
198 private final IdentityHashMap<KT, VT> associatedMap;
200 public IdentityHashMapEntrySet(IdentityHashMap<KT, VT> hm)
[all...] |
| /external/llvm/lib/CodeGen/ |
| CallingConvLower.cpp | 72 MVT ArgVT = Ins[i].VT;
90 MVT VT = Outs[i].VT;
92 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this))
104 MVT VT = Outs[i].VT;
106 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) {
109 << EVT(VT).getEVTString()
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAG.cpp | 62 static const fltSemantics *EVTToAPFloatSemantics(EVT VT) {
63 switch (VT.getSimpleVT().SimpleTy) {
90 bool ConstantFPSDNode::isValueValidForType(EVT VT,
92 assert(VT.isFloatingPoint() && "Can only convert between FP types");
95 if (VT == MVT::ppcf128 ||
102 (void) Val2.convert(*EVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven,
688 EVT VT = cast<VTSDNode>(N)->getVT();
689 if (VT.isExtended()) {
690 Erased = ExtendedValueTypeNodes.erase(VT);
692 Erased = ValueTypeNodes[VT.getSimpleVT().SimpleTy] != 0
[all...] |
| DAGCombiner.cpp | 257 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
261 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
320 /// legalization or if the specified VT is legal.
321 bool isTypeLegal(const EVT &VT) {
323 return TLI.isTypeLegal(VT);
569 EVT VT = N0.getValueType();
574 DAG.FoldConstantArithmetic(Opc, VT,
577 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
581 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
584 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1))
[all...] |
| LegalizeDAG.cpp | 89 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
93 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
181 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
184 unsigned NumMaskElts = VT.getVectorNumElements();
255 EVT VT = CFP->getValueType(0);
258 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
260 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
263 EVT OrigVT = VT;
264 EVT SVT = VT;
[all...] |
| TargetLowering.cpp | 527 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
531 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
532 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
536 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
537 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
631 /// VT must be a legal type.
632 bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
633 assert(isTypeLegal(VT));
[all...] |
| FastISel.cpp | 131 MVT VT = RealVT.getSimpleVT();
132 if (!TLI.isTypeLegal(VT)) {
134 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
135 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
156 Reg = materializeRegForValue(V, VT);
166 unsigned FastISel::materializeRegForValue(const Value *V, MVT VT) {
171 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue())
[all...] |
| LegalizeVectorOps.cpp | 294 EVT VT = Op.getValueType();
297 EVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
310 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
316 EVT VT = Op.getOperand(0).getValueType();
327 unsigned NumElts = VT.getVectorNumElements();
328 EVT EltVT = VT.getVectorElementType();
446 EVT VT = Op.getValueType();
453 assert(VT.isVector() && !Mask.getValueType().isVector()
456 unsigned NumElem = VT.getVectorNumElements();
463 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand |
[all...] |
| ResourcePriorityQueue.cpp | 97 EVT VT = ScegN->getValueType(i);
98 if (TLI->isTypeLegal(VT)
99 && (TLI->getRegClassFor(VT)->getID() == RCId)) {
135 EVT VT = Op.getNode()->getValueType(Op.getResNo());
136 if (TLI->isTypeLegal(VT)
137 && (TLI->getRegClassFor(VT)->getID() == RCId)) {
335 EVT VT = SU->getNode()->getValueType(i);
336 if (TLI->isTypeLegal(VT)
337 && TLI->getRegClassFor(VT)
338 && TLI->getRegClassFor(VT)->getID() == RCId
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAG.h | 356 SDVTList getVTList(EVT VT);
365 SDValue getConstant(uint64_t Val, EVT VT, bool isTarget = false);
366 SDValue getConstant(const APInt &Val, EVT VT, bool isTarget = false);
367 SDValue getConstant(const ConstantInt &Val, EVT VT, bool isTarget = false);
369 SDValue getTargetConstant(uint64_t Val, EVT VT) {
370 return getConstant(Val, VT, true);
372 SDValue getTargetConstant(const APInt &Val, EVT VT) {
373 return getConstant(Val, VT, true);
375 SDValue getTargetConstant(const ConstantInt &Val, EVT VT) {
376 return getConstant(Val, VT, true)
[all...] |
| ValueTypes.h | 392 static MVT getVectorVT(MVT VT, unsigned NumElements) {
393 switch (VT.SimpleTy) {
454 bool operator==(EVT VT) const {
455 return !(*this != VT);
457 bool operator!=(EVT VT) const {
458 if (V.SimpleTy != VT.V.SimpleTy)
461 return LLVMTy != VT.LLVMTy;
482 /// length, where each element is of type VT.
483 static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements) {
484 MVT M = MVT::getVectorVT(VT.V, NumElements)
[all...] |
| FastISel.h | 163 virtual unsigned FastEmit_(MVT VT,
171 virtual unsigned FastEmit_r(MVT VT,
180 virtual unsigned FastEmit_rr(MVT VT,
190 virtual unsigned FastEmit_ri(MVT VT,
200 virtual unsigned FastEmit_rf(MVT VT,
210 virtual unsigned FastEmit_rri(MVT VT,
221 unsigned FastEmit_ri_(MVT VT,
229 virtual unsigned FastEmit_i(MVT VT,
237 virtual unsigned FastEmit_f(MVT VT,
333 unsigned FastEmitZExtFromI1(MVT VT,
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.cpp | 81 EVT ArgVT = Ins[i].VT;
117 EVT VT = Outs[i].VT;
119 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this, -1, -1, false)){
121 << VT.getEVTString() << "\n";
147 EVT ArgVT = Outs[i].VT;
185 EVT VT = Ins[i].VT;
187 if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this, -1, -1, false))
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 58 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
68 EVT VT = Vec.getValueType();
69 assert(VT.is256BitVector() && "Unexpected vector size!");
70 EVT ElVT = VT.getVectorElementType();
71 unsigned Factor = VT.getSizeInBits()/128;
73 VT.getVectorNumElements()/Factor);
107 EVT VT = Vec.getValueType();
108 assert(VT.is128BitVector() && "Unexpected vector size!");
110 EVT ElVT = VT.getVectorElementType();
130 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 93 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
95 if (VT != PromotedLdStVT) {
96 setOperationAction(ISD::LOAD, VT, Promote);
97 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
99 setOperationAction(ISD::STORE, VT, Promote);
100 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
103 MVT ElemTy = VT.getVectorElementType();
105 setOperationAction(ISD::SETCC, VT, Custom);
106 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
107 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom)
[all...] |
| ARMSelectionDAGInfo.cpp | 52 EVT VT = MVT::i32;
66 Loads[i] = DAG.getLoad(VT, dl, Chain,
98 VT = MVT::i16;
101 VT = MVT::i8;
105 Loads[i] = DAG.getLoad(VT, dl, Chain,
121 VT = MVT::i16;
124 VT = MVT::i8;
|
| ARMFastISel.cpp | 177 bool isTypeLegal(Type *Ty, MVT &VT);
178 bool isLoadTypeLegal(Type *Ty, MVT &VT);
181 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr,
184 bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
187 void ARMSimplifyAddress(Address &Addr, EVT VT, bool useAM3);
191 unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
192 unsigned ARMMaterializeInt(const Constant *C, EVT VT);
193 unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT);
194 unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
195 unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg)
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 39 int prefslotOffset(EVT VT) {
41 if (VT==MVT::i1) retval=3;
42 if (VT==MVT::i8) retval=3;
43 if (VT==MVT::i16) retval=2;
135 MVT::SimpleValueType VT = (MVT::SimpleValueType)sctype;
137 setOperationAction(ISD::LOAD, VT, Custom);
138 setOperationAction(ISD::STORE, VT, Custom);
139 setLoadExtAction(ISD::EXTLOAD, VT, Custom);
140 setLoadExtAction(ISD::ZEXTLOAD, VT, Custom);
141 setLoadExtAction(ISD::SEXTLOAD, VT, Custom)
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 454 MVT::SimpleValueType VT;
459 VT = OverloadedVTs[MatchTy];
465 VT == MVT::iAny || VT == MVT::vAny) &&
468 VT = getValueType(TyEl->getValueAsDef("VT"));
470 if (EVT(VT).isOverloaded()) {
471 OverloadedVTs.push_back(VT);
476 if (VT == MVT::isVoid)
479 IS.RetVTs.push_back(VT);
[all...] |
