| /external/libffi/linux-x86/ |
| ffi.h | 6 #define X86 1
9 #include "../src/x86/ffitarget.h"
|
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | 1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
15 #include "X86.h"
49 " fuse, but the X86 backend currently can't"),
95 ? X86::ADJCALLSTACKDOWN64
96 : X86::ADJCALLSTACKDOWN32),
98 ? X86::ADJCALLSTACKUP64
99 : X86::ADJCALLSTACKUP32)),
103 { X86::ADC32ri, X86::ADC32mi, 0 }
[all...] |
| X86RegisterInfo.cpp | 1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
12 // on X86.
17 #include "X86.h"
54 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
60 ? X86::RIP : X86::EIP,
73 StackPtr = X86::RSP;
74 FramePtr = X86::RBP;
77 StackPtr = X86::ESP
[all...] |
| X86FloatingPoint.cpp | 26 #define DEBUG_TYPE "x86-codegen"
27 #include "X86.h"
72 virtual const char *getPassName() const { return "X86 FP Stackifier"; }
118 unsigned Reg = *I - X86::FP0;
213 /// getStackEntry - Return the X86::FP<n> register in register ST(i).
220 /// getSTReg - Return the X86::ST(i) register which contains the specified
223 return StackTop - 1 - getSlot(RegNo) + X86::ST0;
252 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg);
261 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg);
318 return X86::RFP80RegClass.contains(DstReg) |
[all...] |
| X86MCInstLower.cpp | 1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
10 // This file contains code to lower X86 MachineInstrs to their corresponding
246 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
279 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX
[all...] |
| X86Relocations.h | 1 //===-- X86Relocations.h - X86 Code Relocations -----------------*- C++ -*-===//
10 // This file defines the X86 target-specific relocation types.
20 namespace X86 {
21 /// RelocationType - An enum for the x86 relocation codes. Note that
22 /// the terminology here doesn't follow x86 convention - word means
24 /// by JIT or ObjectCode emitters, this is transparent to the x86 code
|
| X86ELFWriterInfo.cpp | 1 //===-- X86ELFWriterInfo.cpp - ELF Writer Info for the X86 backend --------===//
10 // This file implements ELF writer information for the X86 backend.
38 case X86::reloc_pcrel_word:
40 case X86::reloc_absolute_word:
42 case X86::reloc_absolute_word_sext:
44 case X86::reloc_absolute_dword:
46 case X86::reloc_picrel_word:
52 case X86::reloc_pcrel_word:
54 case X86::reloc_absolute_word:
56 case X86::reloc_absolute_word_sext
[all...] |
| X86FrameLowering.cpp | 1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
61 return X86::SUB64ri8;
62 return X86::SUB64ri32;
65 return X86::SUB32ri8;
66 return X86::SUB32ri;
73 return X86::ADD64ri8;
74 return X86::ADD64ri32;
77 return X86::ADD32ri8;
78 return X86::ADD32ri
[all...] |
| X86Subtarget.cpp | 1 //===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
10 // This file implements the X86 specific subclass of TargetSubtargetInfo.
67 // X86-64 in PIC mode.
75 // target is x86-64 or the symbol is definitely defined in the current
171 // For x86 out-of-order targets, back-schedule address computations so
191 if ((EDX >> 15) & 1) { HasCMov = true; ToggleFeature(X86::FeatureCMOV); }
192 if ((EDX >> 23) & 1) { X86SSELevel = MMX; ToggleFeature(X86::FeatureMMX); }
193 if ((EDX >> 25) & 1) { X86SSELevel = SSE1; ToggleFeature(X86::FeatureSSE1); }
194 if ((EDX >> 26) & 1) { X86SSELevel = SSE2; ToggleFeature(X86::FeatureSSE2); }
195 if (ECX & 0x1) { X86SSELevel = SSE3; ToggleFeature(X86::FeatureSSE3);
[all...] |
| X86FastISel.cpp | 1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
16 #include "X86.h"
64 StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
166 // We only handle legal types. For example, on x86-32 the instruction
167 // selector contains all of the 64-bit instructions from x86-64,
187 Opc = X86::MOV8rm;
188 RC = &X86::GR8RegClass;
191 Opc = X86::MOV16rm
[all...] |
| X86ISelDAGToDAG.cpp | 1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86.h"
94 return RegNode->getReg() == X86::RIP;
143 /// ISel - X86 specific code to select X86 machine instructions for
148 /// X86-specific SelectionDAG.
167 return "X86 DAG->DAG Instruction Selection"
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCTargetDesc.cpp | 1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
10 // This file provides X86 specific target descriptions.
212 /// getX86RegNum - This function maps LLVM register identifiers to their X86
216 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
217 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX
[all...] |
| X86AsmBackend.cpp | 1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
34 MCDisableArithRelaxation("mc-x86-disable-arith-relaxation",
35 cl::desc("Disable relaxation of arithmetic instruction for X86"));
47 case X86::reloc_riprel_4byte:
48 case X86::reloc_riprel_4byte_movq_load:
49 case X86::reloc_signed_4byte:
50 case X86::reloc_global_offset_table:
74 return X86::NumTargetFixupKinds;
78 const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
129 case X86::JAE_1: return X86::JAE_4
[all...] |
| X86BaseInfo.h | 1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
11 // the X86 target useful for the compiler back-end and the MC libraries.
26 namespace X86 {
43 } // end namespace X86;
53 // X86 Specific MachineOperand flags.
70 /// See the X86-64 ELF ABI supplement for more details.
77 /// See the X86-64 ELF ABI supplement for more details.
85 /// See the X86-64 ELF ABI supplement for more details.
92 /// See the X86-64 ELF ABI supplement for more details.
109 /// block for the symbol. Used in the x86-64 local dynamic TLS access model
[all...] |
| X86FixupKinds.h | 1 //===-- X86FixupKinds.h - X86 Specific Fixup Entries ------------*- C++ -*-===//
16 namespace X86 {
|
| X86WinCOFFObjectWriter.cpp | 1 //===-- X86WinCOFFObjectWriter.cpp - X86 Win COFF Writer ------------------===//
44 case X86::reloc_riprel_4byte:
45 case X86::reloc_riprel_4byte_movq_load:
48 case X86::reloc_signed_4byte:
|
| /external/eclipse-basebuilder/basebuilder-3.6.2/org.eclipse.releng.basebuilder/plugins/org.eclipse.equinox.launcher.gtk.linux.x86_1.1.2.R36x_v20101019_1345/ |
| launcher.gtk.linux.x86.properties | 11 pluginName = Equinox Launcher Linux X86 Fragment
|
| /external/eclipse-basebuilder/basebuilder-3.6.2/org.eclipse.releng.basebuilder/plugins/org.eclipse.equinox.launcher.win32.win32.x86_1.1.2.R36x_v20101019_1345/ |
| launcher.win32.win32.x86.properties | 11 pluginName = Equinox Launcher Win32 X86 Fragment
|
| /external/llvm/utils/lit/lit/ExampleTests/LLVM.InTree/test/Bar/ |
| dg.exp | 3 if { [llvm_supports_target X86] } {
|
| /external/llvm/utils/lit/lit/ExampleTests/LLVM.OutOfTree/src/test/Foo/ |
| dg.exp | 3 if { [llvm_supports_target X86] } {
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 10 // This defines functionality used to emit comments about X86 instructions to
26 /// EmitAnyX86InstComments - This function decodes x86 instructions and prints
36 case X86::INSERTPSrr:
41 case X86::VINSERTPSrr:
48 case X86::MOVLHPSrr:
53 case X86::VMOVLHPSrr:
60 case X86::MOVHLPSrr:
65 case X86::VMOVHLPSrr:
72 case X86::PSHUFDri:
73 case X86::VPSHUFDri
[all...] |
| /external/llvm/host/include/llvm/Config/ |
| Targets.def | 28 LLVM_TARGET(X86)
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86Disassembler.cpp | 1 //===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===//
10 // This file is part of the X86 Disassembler.
59 namespace X86 {
166 #define ENTRY(x) X86::x,
348 // By default sign-extend all X86 immediates based on their encoding.
356 // Special case those X86 instructions that use the imm8 as a set of
358 if (Opcode != X86::BLENDPSrri && Opcode != X86::BLENDPDrri &&
359 Opcode != X86::PBLENDWrri && Opcode != X86::MPSADBWrri &
[all...] |
| /frameworks/compile/mclinker/ |
| Android.mk | 28 # X86 Code Generation Libraries
30 lib/Target/X86 \
31 lib/Target/X86/TargetInfo
|
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmLexer.cpp | 1 //===-- X86AsmLexer.cpp - Tokenize X86 assembly to AsmTokens --------------===//
107 case '0': RegNo = X86::DR0; break;
108 case '1': RegNo = X86::DR1; break;
109 case '2': RegNo = X86::DR2; break;
110 case '3': RegNo = X86::DR3; break;
111 case '4': RegNo = X86::DR4; break;
112 case '5': RegNo = X86::DR5; break;
113 case '6': RegNo = X86::DR6; break;
114 case '7': RegNo = X86::DR7; break;
|
