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      1 //===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file implements the X86 specific subclass of TargetSubtargetInfo.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #define DEBUG_TYPE "subtarget"
     15 #include "X86Subtarget.h"
     16 #include "X86InstrInfo.h"
     17 #include "llvm/GlobalValue.h"
     18 #include "llvm/Support/Debug.h"
     19 #include "llvm/Support/ErrorHandling.h"
     20 #include "llvm/Support/raw_ostream.h"
     21 #include "llvm/Support/Host.h"
     22 #include "llvm/Target/TargetMachine.h"
     23 #include "llvm/Target/TargetOptions.h"
     24 
     25 #define GET_SUBTARGETINFO_TARGET_DESC
     26 #define GET_SUBTARGETINFO_CTOR
     27 #include "X86GenSubtargetInfo.inc"
     28 
     29 using namespace llvm;
     30 
     31 #if defined(_MSC_VER)
     32 #include <intrin.h>
     33 #endif
     34 
     35 /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
     36 /// current subtarget according to how we should reference it in a non-pcrel
     37 /// context.
     38 unsigned char X86Subtarget::
     39 ClassifyBlockAddressReference() const {
     40   if (isPICStyleGOT())    // 32-bit ELF targets.
     41     return X86II::MO_GOTOFF;
     42 
     43   if (isPICStyleStubPIC())   // Darwin/32 in PIC mode.
     44     return X86II::MO_PIC_BASE_OFFSET;
     45 
     46   // Direct static reference to label.
     47   return X86II::MO_NO_FLAG;
     48 }
     49 
     50 /// ClassifyGlobalReference - Classify a global variable reference for the
     51 /// current subtarget according to how we should reference it in a non-pcrel
     52 /// context.
     53 unsigned char X86Subtarget::
     54 ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const {
     55   // DLLImport only exists on windows, it is implemented as a load from a
     56   // DLLIMPORT stub.
     57   if (GV->hasDLLImportLinkage())
     58     return X86II::MO_DLLIMPORT;
     59 
     60   // Determine whether this is a reference to a definition or a declaration.
     61   // Materializable GVs (in JIT lazy compilation mode) do not require an extra
     62   // load from stub.
     63   bool isDecl = GV->hasAvailableExternallyLinkage();
     64   if (GV->isDeclaration() && !GV->isMaterializable())
     65     isDecl = true;
     66 
     67   // X86-64 in PIC mode.
     68   if (isPICStyleRIPRel()) {
     69     // Large model never uses stubs.
     70     if (TM.getCodeModel() == CodeModel::Large)
     71       return X86II::MO_NO_FLAG;
     72 
     73     if (isTargetDarwin()) {
     74       // If symbol visibility is hidden, the extra load is not needed if
     75       // target is x86-64 or the symbol is definitely defined in the current
     76       // translation unit.
     77       if (GV->hasDefaultVisibility() &&
     78           (isDecl || GV->isWeakForLinker()))
     79         return X86II::MO_GOTPCREL;
     80     } else if (!isTargetWin64()) {
     81       assert(isTargetELF() && "Unknown rip-relative target");
     82 
     83       // Extra load is needed for all externally visible.
     84       if (!GV->hasLocalLinkage() && GV->hasDefaultVisibility())
     85         return X86II::MO_GOTPCREL;
     86     }
     87 
     88     return X86II::MO_NO_FLAG;
     89   }
     90 
     91   if (isPICStyleGOT()) {   // 32-bit ELF targets.
     92     // Extra load is needed for all externally visible.
     93     if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
     94       return X86II::MO_GOTOFF;
     95     return X86II::MO_GOT;
     96   }
     97 
     98   if (isPICStyleStubPIC()) {  // Darwin/32 in PIC mode.
     99     // Determine whether we have a stub reference and/or whether the reference
    100     // is relative to the PIC base or not.
    101 
    102     // If this is a strong reference to a definition, it is definitely not
    103     // through a stub.
    104     if (!isDecl && !GV->isWeakForLinker())
    105       return X86II::MO_PIC_BASE_OFFSET;
    106 
    107     // Unless we have a symbol with hidden visibility, we have to go through a
    108     // normal $non_lazy_ptr stub because this symbol might be resolved late.
    109     if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
    110       return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
    111 
    112     // If symbol visibility is hidden, we have a stub for common symbol
    113     // references and external declarations.
    114     if (isDecl || GV->hasCommonLinkage()) {
    115       // Hidden $non_lazy_ptr reference.
    116       return X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE;
    117     }
    118 
    119     // Otherwise, no stub.
    120     return X86II::MO_PIC_BASE_OFFSET;
    121   }
    122 
    123   if (isPICStyleStubNoDynamic()) {  // Darwin/32 in -mdynamic-no-pic mode.
    124     // Determine whether we have a stub reference.
    125 
    126     // If this is a strong reference to a definition, it is definitely not
    127     // through a stub.
    128     if (!isDecl && !GV->isWeakForLinker())
    129       return X86II::MO_NO_FLAG;
    130 
    131     // Unless we have a symbol with hidden visibility, we have to go through a
    132     // normal $non_lazy_ptr stub because this symbol might be resolved late.
    133     if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
    134       return X86II::MO_DARWIN_NONLAZY;
    135 
    136     // Otherwise, no stub.
    137     return X86II::MO_NO_FLAG;
    138   }
    139 
    140   // Direct static reference to global.
    141   return X86II::MO_NO_FLAG;
    142 }
    143 
    144 
    145 /// getBZeroEntry - This function returns the name of a function which has an
    146 /// interface like the non-standard bzero function, if such a function exists on
    147 /// the current subtarget and it is considered prefereable over memset with zero
    148 /// passed as the second argument. Otherwise it returns null.
    149 const char *X86Subtarget::getBZeroEntry() const {
    150   // Darwin 10 has a __bzero entry point for this purpose.
    151   if (getTargetTriple().isMacOSX() &&
    152       !getTargetTriple().isMacOSXVersionLT(10, 6))
    153     return "__bzero";
    154 
    155   return 0;
    156 }
    157 
    158 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
    159 /// to immediate address.
    160 bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
    161   if (In64BitMode)
    162     return false;
    163   return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
    164 }
    165 
    166 /// getSpecialAddressLatency - For targets where it is beneficial to
    167 /// backschedule instructions that compute addresses, return a value
    168 /// indicating the number of scheduling cycles of backscheduling that
    169 /// should be attempted.
    170 unsigned X86Subtarget::getSpecialAddressLatency() const {
    171   // For x86 out-of-order targets, back-schedule address computations so
    172   // that loads and stores aren't blocked.
    173   // This value was chosen arbitrarily.
    174   return 200;
    175 }
    176 
    177 void X86Subtarget::AutoDetectSubtargetFeatures() {
    178   unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
    179   unsigned MaxLevel;
    180   union {
    181     unsigned u[3];
    182     char     c[12];
    183   } text;
    184 
    185   if (X86_MC::GetCpuIDAndInfo(0, &MaxLevel, text.u+0, text.u+2, text.u+1) ||
    186       MaxLevel < 1)
    187     return;
    188 
    189   X86_MC::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
    190 
    191   if ((EDX >> 15) & 1) { HasCMov = true;      ToggleFeature(X86::FeatureCMOV); }
    192   if ((EDX >> 23) & 1) { X86SSELevel = MMX;   ToggleFeature(X86::FeatureMMX);  }
    193   if ((EDX >> 25) & 1) { X86SSELevel = SSE1;  ToggleFeature(X86::FeatureSSE1); }
    194   if ((EDX >> 26) & 1) { X86SSELevel = SSE2;  ToggleFeature(X86::FeatureSSE2); }
    195   if (ECX & 0x1)       { X86SSELevel = SSE3;  ToggleFeature(X86::FeatureSSE3); }
    196   if ((ECX >> 9)  & 1) { X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3);}
    197   if ((ECX >> 19) & 1) { X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41);}
    198   if ((ECX >> 20) & 1) { X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42);}
    199   if ((ECX >> 28) & 1) { X86SSELevel = AVX;   ToggleFeature(X86::FeatureAVX); }
    200 
    201   bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
    202   bool IsAMD   = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
    203 
    204   if ((ECX >> 1) & 0x1) {
    205     HasPCLMUL = true;
    206     ToggleFeature(X86::FeaturePCLMUL);
    207   }
    208   if ((ECX >> 12) & 0x1) {
    209     HasFMA = true;
    210     ToggleFeature(X86::FeatureFMA);
    211   }
    212   if (IsIntel && ((ECX >> 22) & 0x1)) {
    213     HasMOVBE = true;
    214     ToggleFeature(X86::FeatureMOVBE);
    215   }
    216   if ((ECX >> 23) & 0x1) {
    217     HasPOPCNT = true;
    218     ToggleFeature(X86::FeaturePOPCNT);
    219   }
    220   if ((ECX >> 25) & 0x1) {
    221     HasAES = true;
    222     ToggleFeature(X86::FeatureAES);
    223   }
    224   if ((ECX >> 29) & 0x1) {
    225     HasF16C = true;
    226     ToggleFeature(X86::FeatureF16C);
    227   }
    228   if (IsIntel && ((ECX >> 30) & 0x1)) {
    229     HasRDRAND = true;
    230     ToggleFeature(X86::FeatureRDRAND);
    231   }
    232 
    233   if ((ECX >> 13) & 0x1) {
    234     HasCmpxchg16b = true;
    235     ToggleFeature(X86::FeatureCMPXCHG16B);
    236   }
    237 
    238   if (IsIntel || IsAMD) {
    239     // Determine if bit test memory instructions are slow.
    240     unsigned Family = 0;
    241     unsigned Model  = 0;
    242     X86_MC::DetectFamilyModel(EAX, Family, Model);
    243     if (IsAMD || (Family == 6 && Model >= 13)) {
    244       IsBTMemSlow = true;
    245       ToggleFeature(X86::FeatureSlowBTMem);
    246     }
    247 
    248     // If it's Nehalem, unaligned memory access is fast.
    249     // Include Westmere and Sandy Bridge as well.
    250     // FIXME: add later processors.
    251     if (IsIntel && ((Family == 6 && Model == 26) ||
    252         (Family == 6 && Model == 44) ||
    253         (Family == 6 && Model == 42))) {
    254       IsUAMemFast = true;
    255       ToggleFeature(X86::FeatureFastUAMem);
    256     }
    257 
    258     // Set processor type. Currently only Atom is detected.
    259     if (Family == 6 &&
    260         (Model == 28 || Model == 38 || Model == 39
    261          || Model == 53 || Model == 54)) {
    262       X86ProcFamily = IntelAtom;
    263 
    264       UseLeaForSP = true;
    265       ToggleFeature(X86::FeatureLeaForSP);
    266     }
    267 
    268     unsigned MaxExtLevel;
    269     X86_MC::GetCpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
    270 
    271     if (MaxExtLevel >= 0x80000001) {
    272       X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
    273       if ((EDX >> 29) & 0x1) {
    274         HasX86_64 = true;
    275         ToggleFeature(X86::Feature64Bit);
    276       }
    277       if ((ECX >> 5) & 0x1) {
    278         HasLZCNT = true;
    279         ToggleFeature(X86::FeatureLZCNT);
    280       }
    281       if (IsAMD) {
    282         if ((ECX >> 6) & 0x1) {
    283           HasSSE4A = true;
    284           ToggleFeature(X86::FeatureSSE4A);
    285         }
    286         if ((ECX >> 11) & 0x1) {
    287           HasXOP = true;
    288           ToggleFeature(X86::FeatureXOP);
    289         }
    290         if ((ECX >> 16) & 0x1) {
    291           HasFMA4 = true;
    292           ToggleFeature(X86::FeatureFMA4);
    293         }
    294       }
    295     }
    296   }
    297 
    298   if (MaxLevel >= 7) {
    299     if (!X86_MC::GetCpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX)) {
    300       if (IsIntel && (EBX & 0x1)) {
    301         HasFSGSBase = true;
    302         ToggleFeature(X86::FeatureFSGSBase);
    303       }
    304       if ((EBX >> 3) & 0x1) {
    305         HasBMI = true;
    306         ToggleFeature(X86::FeatureBMI);
    307       }
    308       if (IsIntel && ((EBX >> 5) & 0x1)) {
    309         X86SSELevel = AVX2;
    310         ToggleFeature(X86::FeatureAVX2);
    311       }
    312       if (IsIntel && ((EBX >> 8) & 0x1)) {
    313         HasBMI2 = true;
    314         ToggleFeature(X86::FeatureBMI2);
    315       }
    316     }
    317   }
    318 }
    319 
    320 X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
    321                            const std::string &FS,
    322                            unsigned StackAlignOverride, bool is64Bit)
    323   : X86GenSubtargetInfo(TT, CPU, FS)
    324   , X86ProcFamily(Others)
    325   , PICStyle(PICStyles::None)
    326   , X86SSELevel(NoMMXSSE)
    327   , X863DNowLevel(NoThreeDNow)
    328   , HasCMov(false)
    329   , HasX86_64(false)
    330   , HasPOPCNT(false)
    331   , HasSSE4A(false)
    332   , HasAES(false)
    333   , HasPCLMUL(false)
    334   , HasFMA(false)
    335   , HasFMA4(false)
    336   , HasXOP(false)
    337   , HasMOVBE(false)
    338   , HasRDRAND(false)
    339   , HasF16C(false)
    340   , HasFSGSBase(false)
    341   , HasLZCNT(false)
    342   , HasBMI(false)
    343   , HasBMI2(false)
    344   , IsBTMemSlow(false)
    345   , IsUAMemFast(false)
    346   , HasVectorUAMem(false)
    347   , HasCmpxchg16b(false)
    348   , UseLeaForSP(false)
    349   , HasSlowDivide(false)
    350   , PostRAScheduler(false)
    351   , stackAlignment(4)
    352   // FIXME: this is a known good value for Yonah. How about others?
    353   , MaxInlineSizeThreshold(128)
    354   , TargetTriple(TT)
    355   , In64BitMode(is64Bit) {
    356   // Determine default and user specified characteristics
    357   std::string CPUName = CPU;
    358   if (!FS.empty() || !CPU.empty()) {
    359     if (CPUName.empty()) {
    360 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
    361     || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
    362       CPUName = sys::getHostCPUName();
    363 #else
    364       CPUName = "generic";
    365 #endif
    366     }
    367 
    368     // Make sure 64-bit features are available in 64-bit mode. (But make sure
    369     // SSE2 can be turned off explicitly.)
    370     std::string FullFS = FS;
    371     if (In64BitMode) {
    372       if (!FullFS.empty())
    373         FullFS = "+64bit,+sse2," + FullFS;
    374       else
    375         FullFS = "+64bit,+sse2";
    376     }
    377 
    378     // If feature string is not empty, parse features string.
    379     ParseSubtargetFeatures(CPUName, FullFS);
    380   } else {
    381     if (CPUName.empty()) {
    382 #if defined (__x86_64__) || defined(__i386__)
    383       CPUName = sys::getHostCPUName();
    384 #else
    385       CPUName = "generic";
    386 #endif
    387     }
    388     // Otherwise, use CPUID to auto-detect feature set.
    389     AutoDetectSubtargetFeatures();
    390 
    391     // Make sure 64-bit features are available in 64-bit mode.
    392     if (In64BitMode) {
    393       HasX86_64 = true; ToggleFeature(X86::Feature64Bit);
    394       HasCMov = true;   ToggleFeature(X86::FeatureCMOV);
    395 
    396       if (X86SSELevel < SSE2) {
    397         X86SSELevel = SSE2;
    398         ToggleFeature(X86::FeatureSSE1);
    399         ToggleFeature(X86::FeatureSSE2);
    400       }
    401     }
    402   }
    403 
    404   if (X86ProcFamily == IntelAtom)
    405     PostRAScheduler = true;
    406 
    407   InstrItins = getInstrItineraryForCPU(CPUName);
    408 
    409   // It's important to keep the MCSubtargetInfo feature bits in sync with
    410   // target data structure which is shared with MC code emitter, etc.
    411   if (In64BitMode)
    412     ToggleFeature(X86::Mode64Bit);
    413 
    414   DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
    415                << ", 3DNowLevel " << X863DNowLevel
    416                << ", 64bit " << HasX86_64 << "\n");
    417   assert((!In64BitMode || HasX86_64) &&
    418          "64-bit code requested on a subtarget that doesn't support it!");
    419 
    420   // Stack alignment is 16 bytes on Darwin, FreeBSD, Linux and Solaris (both
    421   // 32 and 64 bit) and for all 64-bit targets.
    422   if (StackAlignOverride)
    423     stackAlignment = StackAlignOverride;
    424   else if (isTargetDarwin() || isTargetFreeBSD() || isTargetLinux() ||
    425            isTargetSolaris() || In64BitMode)
    426     stackAlignment = 16;
    427 }
    428 
    429 bool X86Subtarget::enablePostRAScheduler(
    430            CodeGenOpt::Level OptLevel,
    431            TargetSubtargetInfo::AntiDepBreakMode& Mode,
    432            RegClassVector& CriticalPathRCs) const {
    433   Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
    434   CriticalPathRCs.clear();
    435   return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
    436 }
    437