| /external/llvm/lib/Target/ARM/ |
| ARMRegisterInfo.cpp | 21 ARMRegisterInfo::ARMRegisterInfo(const ARMBaseInstrInfo &tii,
23 : ARMBaseRegisterInfo(tii, sti) {
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| ARMRegisterInfo.h | 28 ARMRegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
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| ARMHazardRecognizer.h | 31 const ARMBaseInstrInfo &TII;
40 const ARMBaseInstrInfo &tii,
44 ScoreboardHazardRecognizer(ItinData, DAG, "post-RA-sched"), TII(tii),
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| Thumb2RegisterInfo.h | 28 Thumb2RegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
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| Thumb2RegisterInfo.cpp | 27 Thumb2RegisterInfo::Thumb2RegisterInfo(const ARMBaseInstrInfo &tii,
29 : ARMBaseRegisterInfo(tii, sti) {
48 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
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| Thumb1RegisterInfo.h | 28 Thumb1RegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
56 const ARMBaseInstrInfo &TII) const;
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| ARMBaseRegisterInfo.h | 77 const ARMBaseInstrInfo &TII;
89 explicit ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
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| /external/llvm/lib/Target/MBlaze/ |
| MBlazeRegisterInfo.h | 40 const TargetInstrInfo &TII;
43 const TargetInstrInfo &tii);
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| MBlazeRegisterInfo.cpp | 45 MBlazeRegisterInfo(const MBlazeSubtarget &ST, const TargetInstrInfo &tii)
46 : MBlazeGenRegisterInfo(MBlaze::R15), Subtarget(ST), TII(tii) {}
107 New = BuildMI(MF,Old->getDebugLoc(),TII.get(MBlaze::ADDIK),MBlaze::R1)
111 New = BuildMI(MF,Old->getDebugLoc(),TII.get(MBlaze::ADDIK),MBlaze::R1)
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| /external/llvm/lib/Target/MSP430/ |
| MSP430RegisterInfo.h | 30 const TargetInstrInfo &TII;
36 MSP430RegisterInfo(MSP430TargetMachine &tm, const TargetInstrInfo &tii);
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| MSP430RegisterInfo.cpp | 36 const TargetInstrInfo &tii)
37 : MSP430GenRegisterInfo(MSP430::PCW), TM(tm), TII(tii) {
123 if (Old->getOpcode() == TII.getCallFrameSetupOpcode()) {
125 TII.get(MSP430::SUB16ri), MSP430::SPW)
128 assert(Old->getOpcode() == TII.getCallFrameDestroyOpcode());
134 TII.get(MSP430::ADD16ri), MSP430::SPW)
146 } else if (I->getOpcode() == TII.getCallFrameDestroyOpcode()) {
152 BuildMI(MF, Old->getDebugLoc(), TII.get(MSP430::SUB16ri),
201 MI.setDesc(TII.get(MSP430::MOV16rr))
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.h | 30 const TargetInstrInfo &TII;
32 SparcRegisterInfo(SparcSubtarget &st, const TargetInstrInfo &tii);
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| SparcRegisterInfo.cpp | 32 const TargetInstrInfo &tii)
33 : SparcGenRegisterInfo(SP::I7), Subtarget(st), TII(tii) {
68 BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
102 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
104 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
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| /external/llvm/lib/CodeGen/ |
| Spiller.cpp | 58 const TargetInstrInfo *tii; member in class:__anon10279::SpillerBase
68 tii = mf.getTarget().getInstrInfo();
136 tii->loadRegFromStackSlot(*mi->getParent(), miItr, newLI->reg, ss, trc,
149 tii->storeRegToStackSlot(*mi->getParent(), llvm::next(miItr),newLI->reg,
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| BranchFolding.h | 29 const TargetInstrInfo *tii,
90 const TargetInstrInfo *TII;
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| /external/llvm/lib/Target/CellSPU/ |
| SPURegisterInfo.h | 31 const TargetInstrInfo &TII;
37 SPURegisterInfo(const SPUSubtarget &subtarget, const TargetInstrInfo &tii);
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| SPURegisterInfo.cpp | 188 const TargetInstrInfo &tii) :
189 SPUGenRegisterInfo(SPU::R0), Subtarget(subtarget), TII(tii)
301 BuildMI(MBB, II, dl, TII.get(SPU::ILr32), tmpReg )
303 BuildMI(MBB, II, dl, TII.get(newOpcode), MI.getOperand(0).getReg())
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonRegisterInfo.h | 47 const HexagonInstrInfo &TII;
49 HexagonRegisterInfo(HexagonSubtarget &st, const HexagonInstrInfo &tii);
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| HexagonRegisterInfo.cpp | 41 const HexagonInstrInfo &tii)
44 TII(tii) {
167 TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) &&
168 !TII.isSpillPredRegOp(&MI)) {
174 if (!TII.isValidOffset(MI.getOpcode(), Offset)) {
196 if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) {
198 TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset);
200 TII.get(Hexagon::ADD_rr),
204 TII.get(Hexagon::ADD_ri)
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXRegisterInfo.h | 39 NVPTXRegisterInfo(const TargetInstrInfo &tii,
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| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.h | 32 const TargetInstrInfo &TII;
34 PPCRegisterInfo(const PPCSubtarget &SubTarget, const TargetInstrInfo &tii);
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| PPCHazardRecognizers.cpp | 74 PPCHazardRecognizer970::PPCHazardRecognizer970(const TargetInstrInfo &tii)
75 : TII(tii) {
94 const MCInstrDesc &MCID = TII.get(Opcode);
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| /external/llvm/lib/Target/X86/ |
| X86RegisterInfo.h | 30 const TargetInstrInfo &TII;
59 X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii);
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| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.h | 28 const TargetInstrInfo &TII;
43 XCoreRegisterInfo(const TargetInstrInfo &tii);
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| XCoreRegisterInfo.cpp | 40 XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
41 : XCoreGenRegisterInfo(XCore::LR), TII(tii) {
139 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
144 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
229 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
234 BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
240 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
250 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
255 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus)
[all...] |
