| /external/llvm/test/CodeGen/CellSPU/useful-harnesses/ |
| vecoperations.c | 7 typedef long long v2i64 __attribute__((ext_vector_type(2))); typedef
58 void print_v2i64(const char *str, v2i64 v) {
126 v2i64 v2i64_shuffle(v2i64 a) {
127 v2i64 c2 = a.yx;
147 v2i64 v3 = { 691043ll, 910301513ll };
|
| /external/llvm/include/llvm/CodeGen/ |
| ValueTypes.h | 73 v2i64 = 27, // 2 x i64 enumerator in enum:llvm::MVT::SimpleValueType
188 SimpleTy == MVT::v4i32 || SimpleTy == MVT::v2i64 ||
250 case v2i64:
286 case v2i64:
329 case v2i64:
417 if (NumElements == 2) return MVT::v2i64;
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.cpp | 220 case MVT::v2i64: Opcode = NVPTX::LD_v2i64_avar; break;
250 case MVT::v2i64: Opcode = NVPTX::LD_v2i64_asi; break;
280 case MVT::v2i64: Opcode = NVPTX::LD_v2i64_ari; break;
309 case MVT::v2i64: Opcode = NVPTX::LD_v2i64_areg; break;
406 case MVT::v2i64: Opcode = NVPTX::ST_v2i64_avar; break;
437 case MVT::v2i64: Opcode = NVPTX::ST_v2i64_asi; break;
468 case MVT::v2i64: Opcode = NVPTX::ST_v2i64_ari; break;
497 case MVT::v2i64: Opcode = NVPTX::ST_v2i64_areg; break;
|
| NVPTXISelLowering.cpp | 96 addRegisterClass(MVT::v2i64, &NVPTX::V2I64RegsRegClass);
106 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64 , Custom);
117 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i64 , Custom);
200 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64 , Custom);
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelDAGToDAG.cpp | 188 ((vecVT == MVT::v2i64) &&
592 case MVT::v2i64:
705 } else if (Opc == ISD::ADD && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
717 } else if (Opc == ISD::SUB && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
729 } else if (Opc == ISD::MUL && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
813 MVT::v2i64,
826 SDValue absVec = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64,
894 * \note This code could also be used to implement v2i64 shl.
[all...] |
| SPUISelLowering.cpp | 405 addRegisterClass(MVT::v2i64, &SPU::VECREGRegClass);
452 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
[all...] |
| /external/llvm/lib/VMCore/ |
| ValueTypes.cpp | 137 case MVT::v2i64: return "v2i64";
188 case MVT::v2i64: return VectorType::get(Type::getInt64Ty(Context), 2);
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 207 DecodeUNPCKHMask(MVT::v2i64, ShuffleMask);
215 DecodeUNPCKHMask(MVT::v2i64, ShuffleMask);
300 DecodeUNPCKLMask(MVT::v2i64, ShuffleMask);
308 DecodeUNPCKLMask(MVT::v2i64, ShuffleMask);
|
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| X86FastISel.cpp | 270 case MVT::v2i64:
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 84 case MVT::v2i64: return "MVT::v2i64";
|
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | [all...] |
| ARMISelLowering.cpp | 467 addQRTypeForNEON(MVT::v2i64);
519 // Neon does not support some operations on v1i64 and v2i64 types.
524 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
531 setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
[all...] |
