Lines Matching refs:v2i64
405 addRegisterClass(MVT::v2i64, &SPU::VECREGRegClass);
452 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
1108 SDValue Tvec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T);
1179 case MVT::v2i64:
1333 case MVT::v2i64:
1701 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T));
1724 case MVT::v2i64: {
1873 maskVT = MVT::v2i64;
1978 case MVT::v2i64: n_copies = 2; VT = MVT::i64; break;
2753 MVT mvt = Op0VT == MVT::i64 ? MVT::v2i64 : MVT::v4i32;
